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Non Volatile Memory IP is Invaluable for PMICs

Non Volatile Memory IP is Invaluable for PMICs
by Tom Simon on 03-07-2022 at 6:00 am

Applications for NVM in PMICs

Power Management ICs are a vitally important part of system design. Evidence of this is cited by a Synopsys white paper that mentions how Apple acquired a portion of PMIC developer Dialog Semiconductor that was previously their exclusive PMIC supplier. Clearly Apple had decided that PMIC design was a strategic differentiating… Read More


Using a GPU to Speed Up PCB Layout Editing

Using a GPU to Speed Up PCB Layout Editing
by Daniel Payne on 03-01-2022 at 10:00 am

3D PCB min

I can remember back in the 1980s how Apollo workstations were quite popular, because they accelerated the graphics display time for EDA tools much better than competitive hardware. Fast forward to 2022 and we have the same promise of speeding up EDA tools like PCB layout editing by using a GPU. At the 58th DAC there was a session called,… Read More


Breker Verification Systems Unleashes the SystemUVM Initiative to Empower UVM Engineering

Breker Verification Systems Unleashes the SystemUVM Initiative to Empower UVM Engineering
by Daniel Nenni on 02-28-2022 at 6:00 am

SystemUVM Language Characteristics

The much anticipated (virtual) DVCON 2022 is happening this week and functional verification plus UVM is a very hot topic.  Functional Verification Engineers using UVM can enjoy a large number of benefits by synthesizing test content for their testbenches. Abstract, easily composable models, coverage-driven content, deep… Read More


CEO Interview: Tamas Olaszi of Jade Design Automation

CEO Interview: Tamas Olaszi of Jade Design Automation
by Daniel Nenni on 02-25-2022 at 6:00 am

Tamas Olaszi

Why does the industry need another register management tool? This is a question that Tamas Olaszi, the founder of Jade Design Automation hears from time to time since Jade-DA brought Register Manager, their EDA tool, to market. So why?

There is a genuine answer to this question but first let me use this interview to give some helpful… Read More


Scalable Verification Solutions at Siemens EDA

Scalable Verification Solutions at Siemens EDA
by Daniel Nenni on 02-24-2022 at 6:00 am

Andy Meier 2

Lauro Rizzatti recently interviewed Andy Meier, product manager in the Scalable Verification Solutions Division at Siemens EDA. Andy is a product manager in the Scalable Verification Solutions Division at Siemens EDA. Andy has held positions in the electronics and high-tech fields during his 20-year career including: Sr.Read More


Working with the Unified Power Format

Working with the Unified Power Format
by Daniel Payne on 02-23-2022 at 10:00 am

UPF design flow min

The Accellera organization created the concept of a Unified Power Format (UPF) back in 2006, and by 2007 they shared version 1.0 so that chip designers would have a standard way to communicate the power intentions of IP blocks and full chips. By 2009 the IEEE received the Accellera donation on UPF , reviewed multiple drafts and published… Read More


Power Analysis in Advanced SoCs. A Siemens EDA Perspective

Power Analysis in Advanced SoCs. A Siemens EDA Perspective
by Bernard Murphy on 02-23-2022 at 6:00 am

Power verification methods min

The success of modern battery-powered products depends as much on useful operating time between charges as on functionality. FinFET process technologies overtook earlier planar CMOS in part because they significantly reduce leakage power. But they exacerbate dynamic power consumption thanks to increased pin capacitances.… Read More


The Clash Between 5G and Airline Safety

The Clash Between 5G and Airline Safety
by Tom Simon on 02-22-2022 at 10:00 am

5G and Airline Safety

For 5G to really deliver on its promise of high bandwidth and good coverage, it needs to use an RF band known as C-Band (3.7 to 4.4 GHz). This band is ideal because its frequency is high enough to offer 100MHz wide channels and also low enough that signal attenuation, especially in urban areas, is minimal.  In 2020 the FCC auctioned off… Read More


Six Essential Steps For Optimizing EDA Productivity

Six Essential Steps For Optimizing EDA Productivity
by Kalar Rajendiran on 02-22-2022 at 6:00 am

Semiconductor Design Phases and Needs

Altair® Accelerator™ was the focus of a couple of SemiWiki posts last year. The most recent post covers the enterprise-grade job scheduler’s latest updates and an earlier one discussed its patented Rapid Scaling feature. You can refer to these blogs here. While these posts provide insight into how Accelerator can help increase… Read More


Automated Documentation of Space-Borne FPGA Designs

Automated Documentation of Space-Borne FPGA Designs
by Daniel Nenni on 02-21-2022 at 10:00 am

Kepler Schem

Over the past three years, I’ve spoken frequently with Cristian Amitroaie, CEO and co-founder of AMIQ EDA, to understand how the company is helping engineers cope with the challenges of chip design and verification. With their broad customer base and many years of experience in the EDA business, the folks at AMIQ really seem to … Read More