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Electronic Design Automation
At SemiWiki we’ve written four times now about how TSMC is standardizing on a 3DIC physical flow with their approach called 3Dblox, so I watched a presentation from John Ferguson of Siemens EDA to see how their tool flow supports this with the Calibre tools. With a chiplet-based packaging flow there are new physical verification… Read More
If, like me, you’ve been paying too little attention to historically less glamorous areas of chip design like packaging, you’ll wake up one day and realize just how much things have changed and continue to advance and how interesting it’s become.
One of the main drivers here is the increasing use of chiplets to counter the decreasing… Read More
On big chip design projects the logic verification effort can be larger than the design effort, taking up to 70% of the project time based on data from the 2022 Wilson Research Group findings. Sadly, the first silicon success rate has gone downwards from 31 percent to just 24 percent in the past 8 years, causing another spin to correct… Read More
Dan is joined by Priyank Shukla, Staff Product Manager for the Synopsys High Speed SerDes IP portfolio. He has broad experience in analog, mixed-signal design with strong focus on high performance compute, mobile and automotive SoCs and he has a US patent on low power RTC design.
Dan explores the use of high-speed SerDes with Priyank.… Read More
John R. Cary is professor of physics at the University of Colorado at Boulder and CTO of Tech-X Corporation. He received his PhD from the University of California, Berkeley, in Plasma Physics. Prof. Cary worked at Los Alamos National Laboratory and the Institute for Fusion Studies at the University of Texas, Austin, prior to joining… Read More
Cliosoft recently hosted a webinar where Carl Grace, a scientist from Lawrence Berkeley National Laboratory (LBNL) talked about a cutting edge project for detecting neutrinos. The project is called the Deep Underground Neutrino Experiment (DUNE) project. Many of us know what a neutron is, but what is a neutrino? Before we get… Read More
A comprehensive report from the US Department of Energy (DOE), “Semiconductor Supply Chain Deep Dive Assessment” (February 2022) calls for a 1000X energy efficiency improvement that is required to maintain future compute requirement needs given a finite amount of world energy production. Energy efficiency is at the top of … Read More
As usual in January we start with a look back at the papers we reviewed last year. Paul Cunningham (GM, Verification at Cadence), Raúl Camposano (Silicon Catalyst, entrepreneur, former Synopsys CTO and now Silvaco CTO) and I continue our series on research ideas. As always, feedback welcome. And don’t forget to come see us at DVCon,… Read More
The semiconductor ecosystem consolidation continues with an interesting acquisition of an EDA company by an IP company. Having worked with both Arteris and Semifore over the past few years I can tell you by personal experience that this is one of those 1+1=3 types of acquisitions, absolutely.
Formal methods for digital verification have advanced enormously over the last couple of decades, mostly in support of verification in control and data transport logic. The popular view had been that datapath logic was not amenable to such techniques. Control/transport proofs depend on property verification; if a proof is … Read More
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Quantum Computing Technologies and Challenges