Many multi-thread consistency problems emerge only in post-silicon testing. Maybe we should take advantage of that fact. Paul Cunningham (Senior VP/GM, Verification at Cadence), Raúl Camposano (Silicon Catalyst, entrepreneur, former Synopsys CTO and now Silvaco CTO) and I continue our series on research ideas. As always,… Read More
Electronic Design Automation
Higher-order QAM and smarter workflows in VSA 2023
3GPP Release 17 and 802.11be (Wi-Fi 7) extend modulation complexity, raising the bar for conformance testing and test instrumentation to new levels. The latest release of Keysight PathWave 89600 Vector Signal Analysis 2023 (VSA 2023) software takes on higher-order QAM and smarter workflows, many customer-requested, for … Read More
The Corellium Experience Moves to EDA
Bill Neifert invited me to join him on Zoom recently to talk about his move to Corellium, a company known within the DevSecOps (development, security, operations) market. Developers and security groups use its virtualization technology to build, test, and secure mobile and IoT apps, firmware, and hardware.
Not knowing much … Read More
New Cadence Joint Enterprise Data and AI Platform Dramatically Accelerates AI-Driven Chip Design Development
Without data, there is no computing field to talk about, no technology world to awe at and not much of a semiconductor industry to work in. There is no argument that data is the foundational piece for everything, has been to date and will continue to be. While processing an application’s input data is essential to serve the intended… Read More
Clock Aging Issues at Sub-10nm Nodes
Semiconductor chips are all tested prior to shipment in order to weed out early failures, however there are some more subtle reliability effects that only appear in the longer term, like clock aging. There’s even a classic chart that shows the “bathtub curve” of failure rates over time:
If reality and expectations… Read More
The Increasing Gap between Semiconductor Companies and their Customers
Semiconductors sit at the heart of the electronics revolution, and the scaling enabled by Moore’s law has had a transformational impact on electronics as well as society. Traditionally, the relationship between semiconductor companies and their customers has been a function of the volume driven by the customer. In very … Read More
Balancing Analog Layout Parasitics in MOSFET Differential Pairs
This article is an abstract of Paul Clewes’ webinar you can find here.
Differential amplifiers apply gain not to one input signal but to the difference between two input signals. This means that a differential amplifier naturally eliminates noise or interference that is present in both input signals. Differential amplification… Read More
STOP Writing RTL for Registers
After almost three decades in the EDA business, it is beyond my comprehension to understand why chip designers still hand-write RTL for complex register maps – chip designs with hundreds of registers and thousands of register fields. In today’s silicon world where software is the key to chip-based product success, it is the register… Read More
The CHIPS and Science Act, Cybersecurity, and Semiconductor Manufacturing
This year is proving to be a momentous one for U.S. semiconductor manufacturing. During a global chip shortage and record inflation, President Biden signed into effect the CHIPS and Science Act – which so far is the greatest boon to U.S. semiconductor manufacturing in history, with $52 billion in subsidies for chip manufacturers… Read More
Podcast EP112: How Cadence is Revolutionizing Full-Chip Signoff with Certus
Dan is joined by Brandon Bautz, Sr. Group Director of Product Management, responsible for the Cadence silicon signoff and verification product lines in the Digital & Signoff Group.
Dan and Brandon explore the substantial challenges faced by design teams needing to perform full-chip signoff at an accelerated pace for advanced… Read More
Should Intel be Split in Half?