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IROC at the TSMC Open Innovation Ecosystem Platform

IROC at the TSMC Open Innovation Ecosystem Platform
by Daniel Nenni on 11-09-2023 at 6:00 am

TSMC OIP IROC

Radiation is everywhere. Radiation contributes to Single Event Effects (SEE) in semiconductor circuits and packaging. As chips get larger, containing more functions, and using lower voltage to reduce power, SEEs have become more significant to product reliability, Failures In Time rates (FIT), and meantime between failures… Read More


Synopsys Debuts RISC-V IP Product Families

Synopsys Debuts RISC-V IP Product Families
by Bernard Murphy on 11-08-2023 at 6:00 am

Synopsys ARC V family min

Synopsys has just announced that it has expanded its ARC processor portfolio to include a family of RISC-V processors. These will be branded under the ARC name as ARC-V and are expected to become available in 2024. This is a significant announcement which I attempt to unpack briefly below.

Why add RISC-V to the portfolio and why now?

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A Fast Path to Better ARC PPA through Fusion Quickstart Implementation Kits and DSO.AI

A Fast Path to Better ARC PPA through Fusion Quickstart Implementation Kits and DSO.AI
by Bernard Murphy on 11-07-2023 at 6:00 am

QIK+DSO.AI flow

Synopsys recently presented a webinar on using their own software to optimize one of their own IPs (an ARC HS68 processor) for both performance and power through what looks like a straightforward flow from initial configuration through first level optimization to more comprehensive AI-driven PPA optimization. Also of note … Read More


Make Your RISC-V Product a Fruitful Endeavor

Make Your RISC-V Product a Fruitful Endeavor
by Daniel Nenni on 11-06-2023 at 6:00 am

RISC V Chip

Consider RISC-V ISA as a new ‘unforbidden fruit’. Unlike other fruits (ISAs) that grow in proprietary orchards, RISC-V is available to all, i.e. open-source. Much like a delicious fruit can be transformed into a wide array of delectable desserts, so can RISC-V be utilized to create a plethora of effective applications across … Read More


Webinar: Fast and Accurate High-Sigma Analysis with Worst-Case Points

Webinar: Fast and Accurate High-Sigma Analysis with Worst-Case Points
by Daniel Payne on 11-02-2023 at 10:00 am

Worst case point min

IC designers are tasked with meeting specifications like robustness in SRAM bit cells where the probability of a violation are lower than 1 part-per-billion (1 ppb). Another example of robustness is a Flip-Flop register that must have a probability of specification violation lower than 1 part-per-million (1 ppm). Using Monte… Read More


Generative AI for Silicon Design – Article 2 (Debug My Waveform)

Generative AI for Silicon Design – Article 2 (Debug My Waveform)
by Anshul Jain on 11-01-2023 at 10:00 am

Generative AI for Silicon Design Article 2

Generative AI has been making waves across various industries, and its potential continues to expand. Among its many applications, one particularly intriguing area is the capacity of GenAI to explain digital design waveforms and act as a co-pilot for hardware engineers in the debugging process. In this article, we will explore

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S2C’s FPGA Prototyping Accelerates the Iteration of XiangShan RISC-V Processor

S2C’s FPGA Prototyping Accelerates the Iteration of XiangShan RISC-V Processor
by Daniel Nenni on 10-30-2023 at 10:00 am

Pic1

S2C announced that the Beijing Institute of Open Source Chip (BOSC) adopted its Prodigy S7-19P Logic System, a VU19P-based FPGA prototyping solution, in the development of the “XiangShan” RISC-V processor. S7-19P not only accelerates the iterations of processor development but also simplifies other companies to realize … Read More


Developing Effective Mixed Signal Models. Innovation in Verification

Developing Effective Mixed Signal Models. Innovation in Verification
by Bernard Murphy on 10-30-2023 at 6:00 am

Innovation New

Mixed-signal modeling is becoming more important as interaction between digital and analog circuitry become more closely intertwined. This level of modeling depends critically on sufficiently accurate yet fast behavioral models for analog components. Paul Cunningham (Senior VP/GM, Verification at Cadence), Raúl Camposano… Read More


Keynote Speakers Announced for IDEAS 2023 Digital Forum

Keynote Speakers Announced for IDEAS 2023 Digital Forum
by Daniel Nenni on 10-26-2023 at 10:00 am

ideas 400X400

As we all know, hearing directly from the people who actually use EDA tools, people who are solving real world problems with the latest technologies are the best source of information. Thus EDA User group meetings are always first on my event list every year which brings us to Ansys Ideas.

Ansys User Group Meeting Features Technical

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Ensuring 3D IC Semiconductor Reliability: Challenges and Solutions for Successful Integration

Ensuring 3D IC Semiconductor Reliability: Challenges and Solutions for Successful Integration
by Kalar Rajendiran on 10-25-2023 at 10:00 am

3D IC Cross Section Illustration

One of the most promising advancements in the semiconductor field is the development of 3D Integrated Circuits (3D ICs). 3D ICs enable companies to partition semiconductor designs and seamlessly integrate silicon Intellectual Property (IP) at the most suitable process nodes and processes. This strategic partitioning yields… Read More