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WP_Term Object
(
    [term_id] => 157
    [name] => EDA
    [slug] => eda
    [term_group] => 0
    [term_taxonomy_id] => 157
    [taxonomy] => category
    [description] => Electronic Design Automation
    [parent] => 0
    [count] => 4079
    [filter] => raw
    [cat_ID] => 157
    [category_count] => 4079
    [category_description] => Electronic Design Automation
    [cat_name] => EDA
    [category_nicename] => eda
    [category_parent] => 0
    [is_post] => 
)

Are EDA companies failing System PCB customers?

Are EDA companies failing System PCB customers?
by Rahul Razdan on 10-31-2022 at 6:00 am

figure1 5

Electronic Design Automation (EDA) is a critical industry which enables the development of electronic systems.  Traditionally, EDA has been bifurcated into two distinctive market segments: Semiconductor and Systems (PCB).   If one were to look at the EDA industry in the early 1970’s, one would find significant capabilities… Read More


Machine Learning Applications in Simulation

Machine Learning Applications in Simulation
by Daniel Nenni on 10-27-2022 at 6:00 am

Xcelium ML min

Machine learning (ML) is finding its way into many of the tools in silicon design flows, to shorten run times and improve the quality of results. Logic simulation seemed an obvious target for ML, though resisted apparent benefits for a while. I suspect this was because we all assumed the obvious application should be to use ML to refine… Read More


Bespoke Silicon Requires Bespoke EDA

Bespoke Silicon Requires Bespoke EDA
by Michiel Ligthart on 10-26-2022 at 10:00 am

Bespoke EDA

When I first heard the term ‘bespoke silicon,’ I had to get my dictionary out. Well versed in the silicon domain, I did not know what bespoke meant. It turns out to be a rather old-fashioned term for tailor made and seems to be very much British English. The word dates from 1583 and is the past participle of bespeak, according… Read More


Post-Silicon Consistency Checking. Innovation in Verification

Post-Silicon Consistency Checking. Innovation in Verification
by Bernard Murphy on 10-26-2022 at 6:00 am

Innovation New

Many multi-thread consistency problems emerge only in post-silicon testing. Maybe we should take advantage of that fact. Paul Cunningham (Senior VP/GM, Verification at Cadence), Raúl Camposano (Silicon Catalyst, entrepreneur, former Synopsys CTO and now Silvaco CTO) and I continue our series on research ideas. As always,… Read More


Higher-order QAM and smarter workflows in VSA 2023

Higher-order QAM and smarter workflows in VSA 2023
by Don Dingee on 10-25-2022 at 10:00 am

Higher-order QAM and smarter workflows in a 5G NR example from the Keysight 89600 VSA

3GPP Release 17 and 802.11be (Wi-Fi 7) extend modulation complexity, raising the bar for conformance testing and test instrumentation to new levels. The latest release of Keysight PathWave 89600 Vector Signal Analysis 2023 (VSA 2023) software takes on higher-order QAM and smarter workflows, many customer-requested, for … Read More


The Corellium Experience Moves to EDA

The Corellium Experience Moves to EDA
by Lauro Rizzatti on 10-25-2022 at 6:00 am

Corellium SemiWIki

Bill Neifert invited me to join him on Zoom recently to talk about his move to Corellium, a company known within the DevSecOps (development, security, operations) market. Developers and security groups use its virtualization technology to build, test, and secure mobile and IoT apps, firmware, and hardware.

Not knowing much … Read More


New Cadence Joint Enterprise Data and AI Platform Dramatically Accelerates AI-Driven Chip Design Development

New Cadence Joint Enterprise Data and AI Platform Dramatically Accelerates AI-Driven Chip Design Development
by Kalar Rajendiran on 10-24-2022 at 10:00 am

1 Cadence Joint Enterprise Data and AI JedAI Platform

Without data, there is no computing field to talk about, no technology world to awe at and not much of a semiconductor industry to work in. There is no argument that data is the foundational piece for everything, has been to date and will continue to be. While processing an application’s input data is essential to serve the intended… Read More


Clock Aging Issues at Sub-10nm Nodes

Clock Aging Issues at Sub-10nm Nodes
by Daniel Payne on 10-20-2022 at 10:00 am

IC failure rate chart, clock aging

Semiconductor chips are all tested prior to shipment in order to weed out early failures, however there are some more subtle reliability effects that only appear in the longer term, like clock aging. There’s even a classic chart that shows the “bathtub curve” of failure rates over time:

If reality and expectations… Read More


The Increasing Gap between Semiconductor Companies and their Customers

The Increasing Gap between Semiconductor Companies and their Customers
by Rahul Razdan on 10-19-2022 at 6:00 am

figure1 4

Semiconductors sit at the heart of the electronics revolution, and the scaling enabled by Moore’s law has had a transformational impact on electronics as well as society.   Traditionally, the relationship between semiconductor companies and their customers has been a function of the volume driven by the customer.  In very … Read More


Balancing Analog Layout Parasitics in MOSFET Differential Pairs

Balancing Analog Layout Parasitics in MOSFET Differential Pairs
by Daniel Nenni on 10-18-2022 at 6:00 am

Teardrop Display
This article is an abstract of Paul Clewes’ webinar you can find here.

Differential amplifiers apply gain not to one input signal but to the difference between two input signals. This means that a differential amplifier naturally eliminates noise or interference that is present in both input signals. Differential amplification… Read More