Semiwiki 400x100 1 final
WP_Term Object
(
    [term_id] => 157
    [name] => EDA
    [slug] => eda
    [term_group] => 0
    [term_taxonomy_id] => 157
    [taxonomy] => category
    [description] => Electronic Design Automation
    [parent] => 0
    [count] => 4047
    [filter] => raw
    [cat_ID] => 157
    [category_count] => 4047
    [category_description] => Electronic Design Automation
    [cat_name] => EDA
    [category_nicename] => eda
    [category_parent] => 0
    [is_post] => 
)

WikiLeaks: Methodics vs IC Manage

WikiLeaks: Methodics vs IC Manage
by Daniel Nenni on 08-21-2011 at 4:00 pm

Human nature never ceases to amaze me. I understand the recent economic turmoil and looming National Debt has thrown us for a loop but please, let us all get some perspective here and in the words of Rodney King, “Can we all get along?”

A clever little scumbag recently registered the domain danielnenni.com and is now hawking event … Read More


Top 5 Reasons for Wasting Power

Top 5 Reasons for Wasting Power
by Paul McLellan on 08-19-2011 at 2:27 pm

Traditionally, David Letterman style, we should really have the top 10 reasons for wasting power in semiconductor design, but here are the five big ones.

Starting with reason #5: Lack of a power gating strategy
Leakage power is a huge proportion of total power and the only way to save leakage power (apart from low leakage cells when… Read More


Aug 25th in Fremont, CA – Hands on Calibre workshop: DRC, LVS, xRC, ERC, DFM

Aug 25th in Fremont, CA – Hands on Calibre workshop: DRC, LVS, xRC, ERC, DFM
by Daniel Payne on 08-18-2011 at 10:30 am

I’ve blogged about the Calibre family of IC design tools before:

Smart Fill replaced Dummy Fill Approach in a DFM Flow
DRC Wiki
Graphical DRC vs Text-based DRC
Getting Real time Calibre DRC Results with Custom IC Editing
Transistor-level Electrical Rule Checking
Who Needs a 3D Field Solver for IC Design?
Prevention is BetterRead More


Fast Track your SoC Design

Fast Track your SoC Design
by Paul McLellan on 08-17-2011 at 5:24 pm

Atrenta has four seminars coming up on SoC realization. More and more design is actually about finding IP and integrating it together at the block level, and then handing it off to a standard RTL to GDSII flow. The three focus areas are:

  • finding quality IP faster
  • accelerating IP integration and SoC assembly
  • handing off RTL successfully.
Read More

ANSYS Regional Conference

ANSYS Regional Conference
by Paul McLellan on 08-17-2011 at 3:15 pm

Next Tuesday, August 23rd, is the ANSYS Regional Conference for Silicon Valley. It takes place at the Techmart Network Meeting Center. Apache has three presentations during the day:

  • 9.25-9.45 Andrew Yang Introducing Apache Design Solutions
  • 11.00-11.30 Methodology for delivering power-efficient designs from concept to
Read More

Solido – Variation Analysis and Design Software for Custom ICs

Solido – Variation Analysis and Design Software for Custom ICs
by Daniel Payne on 08-15-2011 at 7:11 pm

Introduction
When I designed DRAM chips at Intel I wanted to simulate at the worst case process corners to help make my design as robust as possible in order to improve yields. My manager knew what the worst case corners were based on years of prior experience, so that’s what I used for my circuit simulations.… Read More


Cadence VIP Seminar: next stop after Denali party, August 25th in San Jose

Cadence VIP Seminar: next stop after Denali party, August 25th in San Jose
by Eric Esteve on 08-15-2011 at 10:42 am

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If you did not have the chance to attend the famous Denali party at DAC 2011, you may want to go to Cadence VIP seminar to be held on Thursday, August 25, 2011, from 1:00 – 4:15pm at Cadence Headquarters: 2655 Seely Avenue, San Jose, Building 10. To register, click here. The atmosphere could be slightly different, as during DenaliRead More


OPC Model Accuracy and Predictability – Evolution of Lithography Process Models, Part III

OPC Model Accuracy and Predictability – Evolution of Lithography Process Models, Part III
by Beth Martin on 08-15-2011 at 7:00 am

Wyatt Earp probably wasn’t thinking of OPC when he said, “Fast is fine, but accuracy is everything,” but I’ll adopt that motto for this discussion of full-chip OPC and post-OPC verification models.

Accuracy
is the difference between the calibrated model prediction and the calibration wafer result. Accuracy depends on several… Read More


ANSYS/Apache

ANSYS/Apache
by Paul McLellan on 08-13-2011 at 2:43 pm

Last week I met with Andrew Yang, erstwhile CEO of Apache Design Systems and now formally President of Apache Design Inc, a wholly owned subsidiary of ANSYS. The merger formally closed at the start of the month. Within ANSYS Apache is positioned as Chip-aware System-level Engineering Simulation. ANSYS is pretty much completely… Read More