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EDA Tools to Optimize Memory Design

EDA Tools to Optimize Memory Design
by Daniel Payne on 06-21-2012 at 8:15 pm

I met with Amit Gupta, President and CEO of Solido at DAC on Tuesday to get an update on their EDA tools used in the design of memory, standard cells and low-power. In 2012 they’ve expanded to add three new software packages: Memory, Standard Cell, Low Power. They must be doing something right because at DAC this year I see more competitors jumping into the Fast Monte Carlo space.

Amit Gupta on right


Trends – 28nm, 20nm designs have an increased number of corners, 3 or 6 sigma yield analysis increase simulation demands. General problem is to cut back the number of simulations.

New packages – Memory, Std Cell, Low Power suites, all new for 2012.

Pricing – see the sales guy

Memory Suite – 6 sigma (high sigma) MonteCarlo, take the results and predict the yield of the entire memory array. Output shows the trade off between yield of a RAM device and it’s performance.

Q: 7 of top 20 semi companies are using Solido tools to improve their designs.
High sigma MC in a few thousand simulations in 15 minutes or so requires a Circuit Simulator (Cadence, Synopsys, Mentor). Solido controls the simulator and tabulates the results.

Memory Suite uses results of high sigma MC simulation. Fast, accurate scalable, verifiable (directly simulated in your SPICE simulator). HSMC.

Q: If I ran the Memory Suite on Spectre then HSPICE, would the results vary much.

Use model – setup your circuit simulator like always, then Solido will control each run.

Nvidia was in a case study.

What about a live challenge?

Standard Cell Suite – cell optimization across corners, 3 to 6 sigma MC, script driven. 2739X faster than Monte Carlo brute force, determines 4.5 sigma results, FF with up to 224 variables, using real MC samples, cell optimization with 24.1% improvement in FF Tsetup time example, completed in just 15 minutes.

In the TSMC reference flow for variation tools, also GLOBALFOUNDRIES reference flow, co-presentation with GF, inside TSMC theatre three times. Foundry qualified and validated.

Low Power Suite – power analysis of cells across PVT, load, RC. 10,000+ combinations. Too long to simulate all these combinations. Get coverage in fewer simulations in hundreds or a few thousand simulations. Validate accuracy of results by doing brute force MC, or just measure silicon. Results have an error margin. SHows simulation or prediction results, so that you can verify how good the numbers are.

Competitors – mostly in-house methods developed over the years. Original focus was analog designs, now it’s more Std cell, memory and low power. Not optimizing, just reporting back MC results so that you can decide how to optimize or center your design.

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