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Electronic Design Automation
Last week GLOBALFOUNDRIES and Mentor Graphics presented at the Tech Design Forum on how they collaborated on a third generation DFM flow. When I reviewed the slides of the presentation it really struck me on how the old thinking in DRC (Design Rule Checking) of Pass/Fail for layout rules had been replaced with a score represented… Read More
Even if nSys acquisition by Synopsys will not have a major impact on Synopsys’ balance sheet, it is a kind of earthquake in the Verification market landscape. After the Denali acquisition by Cadence in 2010, nSys was most probably the market leader in verification IP, if we look at the independent VIP providers (excluding Cadence).… Read More
The CEO panel at the 2nd GTC wasn’t especially enlightening. The theme was that going forward will require cooperation for success and everyone was really ready to cooperate.
The most interesting concept was Aart talking about moving from what he called “scale complexity” aka Moore’s law to what he … Read More
Verifying circuits on advanced process nodes has always been difficult, and it’s no easier with today’s nanometer CMOS processes. There’s a great paradox in nanometer circuit design and verification. Designers achieve their greatest differentiation when they implement analog, mixed-signal, RF and custom … Read More
Whether you use a gate-first or gate-last High-k Metal Gate implementation, yield will be your #1 concern at 28nm, which makes variation analysis and verification a big challenge. One of the consulting projects I have been working on with the foundries and top fabless semiconductor companies is High-Sigma Monte Carlo (HSMC) … Read More
If you are doing transistor-level IC design then you’ve probably come up against questions like:
In the old days we would hold up the old and new versions of the schematics or IC layout and try to eye-ball what had changed. Now we have an automated… Read More
Introduction
Mentor Graphics and GLOBALFOUNDRIES have been working together for several generations since the 65nm node on making IC designs yield higher. Michael Buehler-Garcia, director of Calibre Design SolutionsMarketing at Mentor Graphics spoke with me by phone today to explain how they are working with GLOBALFOUNDRIES… Read More
Mentor has transferred its Catapult (high level synthesis) product line, including the people, to Calypto. Terms were not disclosed but apparently it is a non-cash deal. Calypto gets the product line. Mentor gets a big chunk of ownership of Calypto. So maybe the right way to look at this is as a partial acquisition of Calypto.
It … Read More
OK, let’s face it, when you think of post-silicon debug then formal verification is not the first thing that springs to mind. But once a design has been manufactured, debugging can be very expensive. As then-CEO of MIPS John Bourgoin said at DesignCon 2006, “Finding bugs in model testing is the least expensive and most desired… Read More
According to trusted sources it costs upwards of $50M to design a 40nm SoC down to the GDS. Semiconductor IP is a fast growing part of that equation and functional verification of that IP is critical. Hardware complexity growth continues to follow Moore’s Law but verification complexity is even more challenging. In fact, IP verification… Read More
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What would you do if you were the CEO of Intel?