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Automating Complex Circuit Checking Tasks

Automating Complex Circuit Checking Tasks
by SStalnaker on 09-20-2012 at 7:24 pm

By Hend Wagieh, Mentor Graphics

At advanced IC technology nodes, circuit designers are now encountering problems such as reduced voltage supply headroom, increased wiring parasitic resistance (Rp) and capacitance (Cp), more restrictive electromigration (EM) rules, latch-up, and electrostatic discharge (ESD) damage,… Read More


Schematic Capture, Analog Fast SPICE, and Analysis Update

Schematic Capture, Analog Fast SPICE, and Analysis Update
by Daniel Payne on 09-20-2012 at 1:10 pm

At the DAC show in June I met with folks at Berkeley DA and heard about their Analog Fast SPICE simulator being used inside of the Tanner EDA tools. With the newest release from Tanner called HiPer Silicon version 15.23 you get a tight integration between:… Read More


Synopsys-Springsoft: Almost Done

Synopsys-Springsoft: Almost Done
by Paul McLellan on 09-19-2012 at 8:01 am

Synopsys announced today that they had completed the two main hurdles to acquiring SpringSoft. Remember, SpringSoft is actually a public Taiwanese company so has to fall in line with Taiwanese rules. The first hurdle is that they have obtained regulatory approval in Taiwan for the acquisition (roughly equivalent to FTC approval… Read More


ASIC Prototyping with 4M to 96M Gates

ASIC Prototyping with 4M to 96M Gates
by Daniel Payne on 09-17-2012 at 9:30 am

I’ve used Aldec tools like their Verilog simulator (Riviera PRO) when teaching a class to engineers at Lattice Semi, so to get an update about the company I spoke with Dave Rinehart recently by phone. A big product announcement by Aldec today is for their ASIC prototyping system with a capacity range of 4 Million to 96 Million… Read More


Chip-Package-System Webinar

Chip-Package-System Webinar
by Paul McLellan on 09-14-2012 at 2:47 pm

Aveek Sarkar presented a webinar on chip-package-system (CPS) earlier this summer. One of the big challenges with low-power electronic systems is that the performance, power and price goals are mutually conflicting. It’s like the old joke about “pick any 2”. But for a real system all need to be optimized. … Read More


Cadence September News: strong IP and VIP focus

Cadence September News: strong IP and VIP focus
by Eric Esteve on 09-14-2012 at 4:25 am

There are three articles on the front page, in the September release of Cadence newsletter, all of them are dedicated to either IP (DDR4), VIP (NVM express VIP being used at Samsung) or Martin Lund. You can read Martin’s interview here and/or take a look at what I write about him this summer. This strong focus on IP, and in fact on Interface… Read More


Samsung Invests in Carbon

Samsung Invests in Carbon
by Paul McLellan on 09-12-2012 at 10:00 am

I’ve talked before about how venture capitalists will no longer invest in EDA companies since the prospect for a huge return just isn’t there any more. By big return I mean an acquisition at hundreds of millions of dollars, like SPC, CCR, Ambit, Cadmos, Simplex. But we all know that chips cannot be designed without software… Read More


Is DDR4 a bridge too far?

Is DDR4 a bridge too far?
by Don Dingee on 09-11-2012 at 8:30 pm

We’ve gone through two decades where the PC market made the rules for technology. The industry faces a question now: Can a new technology go mainstream without the PC?

By now, you’ve certainly read the news from Cadence on their DDR4 IP for TSMC 28nm. They are claiming a PHY implementation that exceeds the data rates specified for … Read More


Hogan University: Second Semester

Hogan University: Second Semester
by Paul McLellan on 09-11-2012 at 7:37 pm

The next event in the Jim Hogan Emerging Companies series (organized by the EDAC Emerging Companies Committee) will be on 17th October at Cadence (I’m guessing in building 5 but I’m sure there will be signs). The specific topic this time will be How to Raise Money and How Not to Spend it. The evening will focus on different… Read More


17th Si2 Conference – October 9 – Santa Clara, CA

17th Si2 Conference – October 9 – Santa Clara, CA
by Daniel Nenni on 09-11-2012 at 8:30 am

This conference will begin with a keynote address by my good friend Jim Hogan, EDA industry pioneer and venture capitalist. Jim has worked in the semiconductor design and manufacturing industry for more than 35 years and is very candid about his experience and vision for the future of EDA. This keynote and Q&A alone is worth … Read More