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Electronic Design Automation
With an HDL-based design methodology many IC engineers code in text languages like SystemVerilog and VHDL, so it’s only natural to use a text-based debug methodology. The expression that, “A picture is worth a thousand words” comes to my mind and in this case a visual debug approach is worth considering for … Read More
You have probably already seen the news: Cadence is acquiring Tensilica for $380M. Cadence has been relatively late to the IP party compared to Synopsys. In contrast, Mentor was early, got into the IP business before it was really profitable and ended up shutting down the business.
Tensilica is quite sizable. It has over 200 licensees,… Read More
At the end of last week I talked to Sanjiv Kaul, the new CEO of Calypto. Just to give a little background for those that haven’t been following along at home, Calypto was founded to try and solve the very hard problem of sequential logical equivalence checking (mostly by people from the engineering team that I managed at Ambit).… Read More
Dr. Paul McLellan and I will be covering CDNLive this week, one of the premier EDA events of the year. Take a look at the agenda and exhibits, this year it looks like a full on Design Automation Conference! There is definitely something for everyone!
Get ready for two full days of content with more than a hundred tracks and keynotes by… Read More
It has be come a cliche to say that “power is the new timing”, the thing that keeps designers up at night and drives the major architectural decisions in big SoCs. Nobody is saying it yet but perhaps “reliability is the new power” will be tomorrow’s received wisdom.
I talked to Adrian Evans of IROCTech… Read More
Tanner EDA is a pleasure to work with, they are big on collaboration and customers absolutely love their tools. With the Synopsys acquisition of SpringSoft, Tanner needs to step up and fill the void of the affordable Laker tools. Take a close look at their new v16 release and let me know how they are doing.
New capabilities for back-end… Read More
We have frequently said in Semiwiki how crucial is it for the SC industry to benefit from high quality PHY IP… even if, from a pure business point of view (MBA minded), PHY IP business does not look so attractive. In fact, to be able to design on-the-edge SerDes and PLL (the two key pieces), you need to build and maintain a highly skilled… Read More
I used my secret powers (being a blogger will get you a press pass) to go to the first day of the SPIE conference on advanced lithography a couple of weeks ago. Everything that happens to with process nodes seems to be driven by lithography, and everything that happens in EDA is driven by semiconductor process. It is the place to find … Read More
During DVCon I met with Steve Bailey to get an update on Mentor’s verification. They were also announcing some new capabilities. I also attended Wally Rhines keynote (primarily about verification of course, since this was DVCon; I blogged about that here) and the Mentor lunch (it was pretty much Mentor all day for me) on the… Read More
Clock gating is one of the most basic weapons in the armoury for reducing dynamic power on a design. All modern synthesis tools can insert clock gating cells to shut down clocking to registers when the contents of the register are not changing. The archetypal case is a register which sometimes loads a new value (when an enable signal… Read More
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Quantum Computing Technologies and Challenges