SILVACO 073125 Webinar 800x100
WP_Term Object
(
    [term_id] => 157
    [name] => EDA
    [slug] => eda
    [term_group] => 0
    [term_taxonomy_id] => 157
    [taxonomy] => category
    [description] => Electronic Design Automation
    [parent] => 0
    [count] => 4182
    [filter] => raw
    [cat_ID] => 157
    [category_count] => 4182
    [category_description] => Electronic Design Automation
    [cat_name] => EDA
    [category_nicename] => eda
    [category_parent] => 0
    [is_post] => 
)

Semiconductor PLM – Needs to be smart for techies

Semiconductor PLM – Needs to be smart for techies
by Pawan Fangaria on 04-18-2013 at 8:15 pm

During my long career in semiconductor, EDA, I have heard, believed and experienced that this is a knowledge industry swamped with rapid innovation and technology drivers; typical manufacturing product development processes like Gantt charts and others do not apply here. The fallback is that most of the time estimations are… Read More


Denali+Tensilica+Cosmic = Cadence

Denali+Tensilica+Cosmic = Cadence
by Paul McLellan on 04-17-2013 at 1:00 am

I won’t be able to attend Chris Rowen’s presentation here at the GlobalPress Electronic Summit since I’m going to the first day of the Linley Mobile Microprocessor conference. In fact I wonder if Chris himself will make it since he was running in the Boston marathon on Monday. He finished about 10 minutes before… Read More


Atrenta, Forte and Jasper LOVE DAC

Atrenta, Forte and Jasper LOVE DAC
by Paul McLellan on 04-16-2013 at 8:20 pm

I LOVE DAC is back. This year the sponsors are Atrenta, Jasper and Forte (hey, all semiwiki subscribers). The way it works is that you register on the DAC website here and you get a free three-day exhibit pass. In addition to everything going on in the exhibit hall, including the pavilion panels held there, the pass also gives access… Read More


Wally Rhines: Embedded Software the Next Revolution?

Wally Rhines: Embedded Software the Next Revolution?
by Paul McLellan on 04-16-2013 at 8:10 pm

As seems to be traditional, Wally Rhines gave a keynote here at the GlobalPress Electronics Summit here in sunny Santa Cruz. It was entitled Embedded Software, the Next Revolution in EDA. Unlike Cadence and Synopsys, Mentor has a strong position in embedded software. It has been build up over a long time through a series of acquisitions… Read More


FinFETs: Ask the Experts II!

FinFETs: Ask the Experts II!
by Daniel Nenni on 04-16-2013 at 7:45 pm

As I have mentioned 28 times already, on Friday (April 19[SUP]th[/SUP]) I will be keynoting FinFET day at the EDPS conference in Monterey. This is an excellent opportunity to ask the experts about the challenges of FinFET design and manufacturing in an intimate setting (60 people). If you are interested register today and use theRead More


Webinar: Making a Simple, Structured and Efficient VHDL Testbench

Webinar: Making a Simple, Structured and Efficient VHDL Testbench
by Daniel Nenni on 04-16-2013 at 1:47 am

logo bitvis

Most simple testbenches have close to no structure, are terrible to modify and hopeless to understand. They often take far too much time to implement and provide close to no support when debugging potential problems. This webinar will demonstrate how to build a far better testbench with respect to all these issues – in significantlyRead More


Variation-aware IC Design

Variation-aware IC Design
by Daniel Payne on 04-15-2013 at 4:18 pm

We’ve blogged before about Layout Dependent Effects (LDE) on SemiWiki and how it further complicates the IC design and layout process, especially at 28nm and lower nodes because the IC layout starts to change the MOS device performance. There’s an interesting webinarfrom Cadence on Variation-aware IC Design, … Read More


Chasing DP Rabbits

Chasing DP Rabbits
by SStalnaker on 04-15-2013 at 4:00 pm

“Now, here, you see, it takes all the running you can do, to keep in the same place. If you want to get somewhere else, you must run at least twice as fast as that!”
—Lewis Carroll, Through the Looking Glass

The use of stitching can greatly reduce the number of double patterning (DP) decomposition violations that a designer has to resolve.… Read More


Two New TSMC-Cadence Webinars for Advanced Node Design

Two New TSMC-Cadence Webinars for Advanced Node Design
by Daniel Payne on 04-15-2013 at 3:43 pm

Foundries and EDA vendors are cooperating at increasing levels of technical intimacy as we head to the 20nm and lower nodes. Cadence has a strong position in the EDA tools used for IC design and layout of custom and AMS (Analog Mixed-Signal) designs. They have created a series of webinars to highlight the design challenges and new… Read More


FinFETs: Ask the Experts!

FinFETs: Ask the Experts!
by Daniel Nenni on 04-14-2013 at 4:00 pm

On Friday (April 19[SUP]th[/SUP]) I will be keynoting FinFET day at the EDPS conference in Monterey. This is an excellent opportunity to ask the experts about the challenges of FinFET design and manufacturing in an intimate setting (60 people). If you are interested register today and use the promo codeSemiWiki-EDPS-JFR and … Read More