In this tough economy you may find yourself displaced and looking for the next opportunity. If you’d like to add some new EDA tool skills, then check out what EMA Design Automation is offering with free Cadence OrCAD training.… Read More
Electronic Design Automation
Virtual Prototype your SoC including Arteris FlexNoC and optimize architecture using CPAK from Carbon
I have talked about Virtual Prototyping a SoC including FlexNoC Network on Chip IP from Arteris by using Carbon Design Systems set of tools in a previous post. A blog, posted on Carbon’ web, is clearly explaining the process to follow to optimize a fabric (FlexNoC) successively using the different tools from Carbon. Bill Neifert,… Read More
Automating Complex Circuit Checking Tasks
By Hend Wagieh, Mentor Graphics
At advanced IC technology nodes, circuit designers are now encountering problems such as reduced voltage supply headroom, increased wiring parasitic resistance (Rp) and capacitance (Cp), more restrictive electromigration (EM) rules, latch-up, and electrostatic discharge (ESD) damage,… Read More
Schematic Capture, Analog Fast SPICE, and Analysis Update
At the DAC show in June I met with folks at Berkeley DA and heard about their Analog Fast SPICE simulator being used inside of the Tanner EDA tools. With the newest release from Tanner called HiPer Silicon version 15.23 you get a tight integration between:… Read More
Synopsys-Springsoft: Almost Done
Synopsys announced today that they had completed the two main hurdles to acquiring SpringSoft. Remember, SpringSoft is actually a public Taiwanese company so has to fall in line with Taiwanese rules. The first hurdle is that they have obtained regulatory approval in Taiwan for the acquisition (roughly equivalent to FTC approval… Read More
ASIC Prototyping with 4M to 96M Gates
I’ve used Aldec tools like their Verilog simulator (Riviera PRO) when teaching a class to engineers at Lattice Semi, so to get an update about the company I spoke with Dave Rinehart recently by phone. A big product announcement by Aldec today is for their ASIC prototyping system with a capacity range of 4 Million to 96 Million… Read More
Chip-Package-System Webinar
Aveek Sarkar presented a webinar on chip-package-system (CPS) earlier this summer. One of the big challenges with low-power electronic systems is that the performance, power and price goals are mutually conflicting. It’s like the old joke about “pick any 2”. But for a real system all need to be optimized. … Read More
Cadence September News: strong IP and VIP focus
There are three articles on the front page, in the September release of Cadence newsletter, all of them are dedicated to either IP (DDR4), VIP (NVM express VIP being used at Samsung) or Martin Lund. You can read Martin’s interview here and/or take a look at what I write about him this summer. This strong focus on IP, and in fact on Interface… Read More
Samsung Invests in Carbon
I’ve talked before about how venture capitalists will no longer invest in EDA companies since the prospect for a huge return just isn’t there any more. By big return I mean an acquisition at hundreds of millions of dollars, like SPC, CCR, Ambit, Cadmos, Simplex. But we all know that chips cannot be designed without software… Read More
Is DDR4 a bridge too far?
We’ve gone through two decades where the PC market made the rules for technology. The industry faces a question now: Can a new technology go mainstream without the PC?
By now, you’ve certainly read the news from Cadence on their DDR4 IP for TSMC 28nm. They are claiming a PHY implementation that exceeds the data rates specified for … Read More
Real men have fabs!