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TSMC’s DFM Announcement

TSMC’s DFM Announcement
by glforte on 10-14-2010 at 4:00 pm

If you are a TSMC customer, no doubt you have heard TSMC is requiring lithography and planarity analysis for all 45nm designs. Their website says customers can either run it themselves, or contract TSMC services to do it. The most cost-effective way would be for the customers to run it themselves, but some might not have the resources… Read More


So, Why Not Just Write Better Rules?

So, Why Not Just Write Better Rules?
by glforte on 10-14-2010 at 4:00 pm

In my submission about TSMC making some DFM analysis steps mandatory at 45nm (see “TSMC’s DFM Announcement”), I ended with a question about why the foundries can’t just write better design rules (and rule decks) to make sure all designs yield well. Here’s my take on this complicated question.… Read More


TSMC’s DFM Announcement

TSMC’s DFM Announcement
by glforte on 10-14-2010 at 4:00 pm

If you are a TSMC customer, no doubt you have heard TSMC is requiring lithography and planarity analysis for all 45nm designs. Their website says customers can either run it themselves, or contract TSMC services to do it. The most cost-effective way would be for the customers to run it themselves, but some might not have the resources… Read More


So, Why Not Just Write Better Rules?

So, Why Not Just Write Better Rules?
by glforte on 10-14-2010 at 4:00 pm

In my submission about TSMC making some DFM analysis steps mandatory at 45nm (see “TSMC’s DFM Announcement”), I ended with a question about why the foundries can’t just write better design rules (and rule decks) to make sure all designs yield well. Here’s my take on this complicated question.… Read More


Effects of Inception

Effects of Inception
by glforte on 10-14-2010 at 10:00 am

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I finally got to watch the critically acclaimed sci-fi movie “Inception” last weekend and life has not been the same since. Without giving away too much detail for the benefit of those who have not watched it yet, the main plot involves dreams within dreams within dreams – three levels to be precise—to “incept” an idea into … Read More


TSMC OIP Conference 2010 Critique!

TSMC OIP Conference 2010 Critique!
by Daniel Nenni on 10-10-2010 at 10:18 pm

Okay, this is more of a, “What I would do if I was TSMC” than a critique, but I needed a one word descriptor for the title. This was the third TSMC OIP Conference and I would guess about 250 people attended. This was the first time I have seen TSMC in “reactive” mode versus “proactive” leadership mode, so I was a bit disappointed. TSMC is … Read More


Critical Area Analysis and Memory Redundancy

Critical Area Analysis and Memory Redundancy
by SStalnaker on 10-08-2010 at 8:08 pm

Simon Favre, one of our Calibre Technical Marketing Engineers, presented a paper on Critical Area Analysis and Memory Redundancy at the 2010 IEEE North Atlantic Test Workshop in Hopewell Junction, NY, just up the road from Fishkill. As Simon says…

Fishkill, New York. IBM is in Fishkill. IBM invented Critical Area Analysis in what,… Read More


Semiconductor Realization!

Semiconductor Realization!
by Daniel Nenni on 09-20-2010 at 1:15 pm

Insanity is doing the same thing over and over again and expecting different results (Albert Einstein). Given that statement, according to John Bruggeman (Cadence CMO and EDA360 Chief Anarchist) the semiconductor industry is INSANE!

This year the EDA Tech Forum and the Global Semiconductor Alliance Expo were not only on the … Read More


GlobalFoundries Exposed, Part II!

GlobalFoundries Exposed, Part II!
by Daniel Nenni on 09-12-2010 at 10:02 pm

EDA CEO panels are usually rather dull but this one definitely held my interest. It was standing room only and I was surrounded by familiar faces from not only EDA and IP company executives, but also representatives from the top semiconductor companies around the world! The theme of course was collaboration, promoting the GFI “IDM-Like”… Read More


Atrenta Semiconductor Design in 3D!

Atrenta Semiconductor Design in 3D!
by Daniel Nenni on 06-27-2010 at 7:04 pm

My vote for most compelling technology at #47DAC is 3D technology. No, I don’t mean Hollywood-style 3D, I’m talking about vertical stacked-die system on chip design. This design approach basically means putting different parts of the system on different silicon substrates, so you can use the right technology for each part, and… Read More