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ClioSoft at GenApSys

ClioSoft at GenApSys
by Paul McLellan on 08-06-2013 at 12:51 pm

GenApSys is a biotech company developing proprietary DNA sequencing technology. As part of that they develop their own custom sequencing chips. These have an analog component and like many people they use the Cadence Virtuoso analog design environment for this.

I talked to Hamid Rategh who is GenApSys’s VP engineering.… Read More


A Brief History of Docea Power

A Brief History of Docea Power
by Daniel Payne on 08-02-2013 at 2:55 pm



Founders

The founder, Ghislain Kaiser, spent about 10 years at STMicroelectronics, mainly in multimedia groups and for the wireless market. At this time, he was a power expert and tasked with making the chips use less power. The first thing he did was to look at what tools existed on the market. They wanted to use off the shelf tools… Read More


Scan the horizon, P1687 takes us higher

Scan the horizon, P1687 takes us higher
by Don Dingee on 07-31-2013 at 6:00 pm

The tech standards cycle almost always goes like this: Problems or limits develop with the existing way of doing things. Innovators attempt to engineer solutions, usually many of them. Chaos ensues when customers figure out nothing new works with anything else. Competitors sit down and agree on a specification where things work… Read More


Pre-verified, Integrated Sensor IP Subsystem?

Pre-verified, Integrated Sensor IP Subsystem?
by Eric Esteve on 07-31-2013 at 11:16 am

Last year, I said that the launch of ARC based complete sound system IP by Synopsys ring the bell for the opening of a new IP market segment, the “Subsystem IP”. This week, Synopsys has announced the availability of the DesignWare® Sensor IP Subsystem, a complete and integrated hardware and software solution for sensor control applications.… Read More


Power and Reliability Sign-off – A must, but how?

Power and Reliability Sign-off – A must, but how?
by Pawan Fangaria on 07-29-2013 at 11:00 am

At the onset of SoCs with multiple functionalities being packed together at the helm of technologies to improve upon performance and area; power, which was earlier neglected, has become critical and needs special attention in designing SoCs. And there comes reliability considerations as well due to multiple electrical and … Read More


What Applications Implement Best with High Level Synthesis?

What Applications Implement Best with High Level Synthesis?
by Daniel Payne on 07-26-2013 at 3:12 pm

RTL coding using languages like Verilog and VHDL have been around since the 1980’s and for almost as long a time we’ve been hearing about High Level Synthesis, or HLS that allows an SoC designer to code above the RTL level where you code at the algorithm level. The most popular HLS languages today are C, C++ and SystemC.… Read More


System Reliability Audits

System Reliability Audits
by Paul McLellan on 07-25-2013 at 12:09 pm

How reliable is your cell-phone? Actually, you don’t really care. It will crash from time to time due to software bugs and you’ll throw it away after two or three years. If a few phones also crash due to stray neutrons from outer space or stray alpha particles from the solder balls used in the flip-chip bonding then nobody… Read More


From Layout Sign-off to RTL Sign-off

From Layout Sign-off to RTL Sign-off
by Pawan Fangaria on 07-25-2013 at 5:00 am

This week, I had a nice opportunity meeting Charu Puri, Corporate Marketing and Sushil Gupta, V.P. & Managing Director at Atrenta, Noida. Well, I know Sushil since 1990s; in fact, he was my manager at one point of time during my job earlier than Cadence. He leads this large R&D development centre, consisting about 200 people… Read More