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Electronic Design Automation
The smaller the process node the more necessary it is that you extract accurate parasitics from interconnect and 3D structures in order to analyze timing, thermal effects and ESD compliance. Silicon Frontlinehas EDA tools in all three of these categories, so I met with Dermott Lynchat DAC to get an annual update.
Dermott Lynch,… Read More
Aart de Geus gave one of the visionary look to the next 50 years of EDA as a warmup to Stephen Wu’s keynote. EDA is enabling the greatest push-pull ever, part of an exponential change on a scale never before seen.
Technologies seem to go through a 50 year technical push phase (driven by improving the technology) followed by a 50… Read More
I first met Michael Munseyback at Viewlogic in the 1990’s, so was pleased to meet with him at DACand get an update on what Dassault Systemes has to offer the EDA world.
Michael Munsey, Dassault Systemes
With EDA tool development in San Jose, Beijing and China, ProPlusis probably best known for their device modeling software called BSIMProPlus. At DAC I met with Lianfeng Yang, Ph.D. the VP of Marketing to hear about what’s new.
Lianfeng Yeng, ProPlus
… Read More
I’m keenly interested in SPICE circuit simulators, so at DACI met with John Piercefrom Cadence to get an update on what’s new this year.
John Pierce, Cadence
… Read More
Kathryn Kranen, CEO of Jasper Design Automation, got to give her view of the future of EDA on the Thursday of DAC. For many years she has been on the EDAC board and is currently chair. When she first was on the board she talked to many of the stakeholders in the EDA ecosystem: EDA companies, IP companies, semiconductor companies, academics,… Read More
If you’re involved with AMS or transistor-level IC design then having visual tools will help you design and debug quicker. At DAC I met with Gerhard Angst, President and Founder of Concept Engineering to get an update.
Gerhard Angst (center), Concept Engineering… Read More
ASIC prototyping from multiple vendors using FPGA boards was popular at DAC again this year in Austin, Texas. I stopped by the Tektronix booth for a few minutes to meet with Dave Orecchio to get an update.
Dave Orecchio (right), Tektronix… Read More
Synopsys has been acquiring EDA and IP companies at a fast clip over the past few years and it’s often made me wonder how they are going to craft a coherent tool flow for custom IC design. At DACthis year I learned that for schematic capture the winning tool is Custom Designer SE– a relatively new tool, while the IC layout… Read More
In Part 1 of this topic I discussed what it takes to estimate the mean time between failures (MTBF) of a single stage synchronizer. Because supply voltages are decreasing and transistor thresholds have been pushed up to minimize leakage, the shortened MTBF of many synchronizer circuits at nanoscale process nodes is presenting… Read More
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Flynn Was Right: How a 2003 Warning Foretold Today’s Architectural Pivot