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EDA

Electronic Design Automation

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The fixed and the finite: QoR in FPGAs

The fixed and the finite: QoR in FPGAs
by Don Dingee on 07-22-2013 at 1:00 pm
Categories: EDA, FPGA, Synopsys

There is an intriguingly amorphous term in FPGA design circles lately: Quality of Results, or QoR. Fitting a design in an FPGA is just the start – is a design optimal in real estate, throughput, power consumption, and IP reuse? Paradoxically, as FPGAs get bigger and take on bigger signal processing problems, QoR has become a larger… Read More

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Efficient Power Analysis and Reduction at RTL Level

Efficient Power Analysis and Reduction at RTL Level
by Pawan Fangaria on 07-22-2013 at 12:30 am
Categories: Ansys, Inc., EDA

It’s a classic and creative example of design and EDA tool community getting together, exploiting tool capabilities and developing flows which add value to all stake holders including the end consumer. We know power has become extremely important for battery life in smart phones, high performance servers, workstations, notebooks… Read More

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New Book on Design Constraints

New Book on Design Constraints
by Paul McLellan on 07-20-2013 at 10:18 pm
Categories: Ansys, Inc., EDA

There is a new book out from Springer. The subtitle is actually a better description that the title. The subtitle is A Practical Guide to Synopsys Design Constraints (SDC) but the title isConstraining Designs for Synthesis and Timing Analysis. The authors are Sridhar Gangadharan of Atrenta in San Jose and Sanjay Churiwala of Xilinx… Read More

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Configurable System IP from a Tool Provider

Configurable System IP from a Tool Provider
by Randy Smith on 07-18-2013 at 11:00 pm
Categories: EDA

While I have previously blogged on Forte’s Cynthesizer Workbench’s Interface Generator, I want to take another look from a different perspective. Watching the tool and IP together in action through public videos provided by Forte it struck me as odd what I did not consider earlier, on what should have been obvious to me – Forte is… Read More

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Oasys Bakes a PIE

Oasys Bakes a PIE
by Paul McLellan on 07-17-2013 at 3:01 pm
Categories: EDA

One challenge in building a modern SoC is that you want to minimize power, performance and area (PPA) while still getting your chip to market on schedule. Realistically, you can’t actually minimize all of these at once since they are tradeoffs: speeding up a critical path often involves upsizing drivers to larger cells which… Read More

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Mixed Signal SOC verification Webinar

Mixed Signal SOC verification Webinar
by Daniel Payne on 07-16-2013 at 8:29 pm
Categories: Concept Engineering, EDA

When looking at the time to design and verify an SoC we’ve known for many years now that the verification effort requires more time than the design process. So anything that will shorten the verification effort will have the biggest impact on keeping your project on schedule.

A second trend is the amount of Analog content in… Read More

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VIA Adopts Cliosoft

VIA Adopts Cliosoft
by Paul McLellan on 07-16-2013 at 4:27 pm
Categories: Cliosoft, EDA

VIA Telecom, who makes CDMA base-band processor chips, picked ClioSoft SOS for use by its analog mixed-signal design teams. Like many such teams they use Cadence’s Virtuoso layout platform. ClioSoft’s SOS is seamlessly integrated into Virtuoso so that designers don’t really need to spend much time worrying… Read More

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Minimize the Cost of Testing ARM® Processor-based Designs and Other Multicore SoCs

Minimize the Cost of Testing ARM® Processor-based Designs and Other Multicore SoCs
by Daniel Payne on 07-15-2013 at 1:37 pm
Categories: EDA, FPGA, Synopsys

On my first job out of college as an IC design engineer I was surprised to discover that a major cost of chips was in the amount of time spent on the tester before being shipped. That is still true today, so how would you keep your tester time down, test coverage high and with a minimum number of pins when using multiple processors on a single… Read More

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Testing an IC Sandwich

Testing an IC Sandwich
by Beth Martin on 07-12-2013 at 3:10 pm
Categories: EDA

At a lovely, but chilly, 3DIncites awards breakfast during SEMICON West, I saw Mentor Graphics win in two of five categories (Calibre 3DSTACK was the other winner). Afterwards, I talked to Steve Pateras, the product marketing director of Mentor’s test solutions about Tessent Memory BIST, which was one of the winners. I asked Pateras… Read More

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Aldec Verifies Compatibility of Northwest Logic’s PCI Express Cores with HES-7™ SoC/ASIC Prototyping Platform

Aldec Verifies Compatibility of Northwest Logic’s PCI Express Cores with HES-7™ SoC/ASIC Prototyping Platform
by Daniel Nenni on 07-12-2013 at 12:50 am
Categories: Aldec, EDA

Henderson, Nevada – July 11, 2013 –Aldec, Inc., a pioneer in mixed HDL language simulation and hardware-assisted verification solutions, today announced that engineers incorporating high-speed PCI Express data transmission into their SoC and ASIC designs can accelerate their time-to-market utilizing Northwest Logic… Read More