hip webinar automating integration workflow 800x100 (1)
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EDA

Electronic Design Automation

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So, where are all the EMBEDDED guys?

So, where are all the EMBEDDED guys?
by Don Dingee on 06-12-2013 at 8:15 pm
Categories: EDA, Events

Roaming the aisles at #50DAC the past week left me with one unmistakable impression: there were two shows going on at the same time. Oh, we were all packed into one space together at the Austin Convention Center and neighboring hotels. But we weren’t quite all speaking the same language – yet.… Read More

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Hardware Assisted Verification

Hardware Assisted Verification
by Paul McLellan on 06-10-2013 at 9:00 pm
Categories: Cadence, EDA, Events, Siemens EDA, Synopsys

On the Tuesday of DAC I moderated a panel session on Hardware Assisted Verification in 10 Years: More Need, More Speed. Although this topic obviously could include FPGA-based prototyping, in fact we spent pretty much the whole time talking about emulation. Gary Smith, on Sunday night, actually set up things by pointing out that… Read More

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Custom Physical IC Design update from Cadence

Custom Physical IC Design update from Cadence
by Daniel Payne on 06-10-2013 at 8:05 pm
Categories: Cadence, EDA

Custom IC design and layout is becoming more difficult at 20nm and smaller nodes, so the EDA tools have to get smarter and work harder for us in order to maintain productivity with the fewest iterations to reach our specs. Dave Stylesand John Stabenow of Cadence met with me last Monday in Austin at the DAC exhibit area.


John Stabenow… Read More

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AMS IC Simulation Update from Synopsys at DAC

AMS IC Simulation Update from Synopsys at DAC
by Daniel Payne on 06-10-2013 at 6:19 pm
Categories: EDA, Synopsys

Last year at DAC we didn’t really know the circuit simulation roadmap for Synopsys because of all the EDA company acquisitions, however this year it’s clear to me that:

  • HSPICE continues on, although it’s a lower performance circuit simulator than FineSim
  • FineSim from Magma is well-loved, and faster than HSPICE
… Read More
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Using Releases for Analog IC Design

Using Releases for Analog IC Design
by Daniel Payne on 06-10-2013 at 1:11 pm
Categories: EDA, Perforce

In a typical analog IC design team, multiple engineers and layout professionals work on cells and libraries. At various points during the design process they will commit changes to their designs into the Design Management (DM) system that manages their files – be it Subversion, Perforce or some other commercial tool.

Using the… Read More

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SoC Sign-off, Real Intent at DAC

SoC Sign-off, Real Intent at DAC
by Daniel Payne on 06-09-2013 at 8:10 pm
Categories: EDA, Events

Monday morning at DAC I met with Real Intent to get an update on their SoC sign-off tools:

  • Dr. Prakash Narain, President and CEO
  • Graham Bell, Sr. Dir. Mktg.

Years ago Prakash was at IBM the only two years that they attended DAC, in an attempt to offer their internal EDA tools to the EDA marketplace. Graham worked at Nassda marketing the… Read More

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IC Design for Implantable Devices Treating Epilepsy

IC Design for Implantable Devices Treating Epilepsy
by Daniel Payne on 06-09-2013 at 8:05 pm
Categories: Concept Engineering, EDA

I’m utterly amazed at how IC-based products are improving our quality of life by implantable devices. The modern day pacemaker has given people added years of life by electrically stimulating the heart. A privately-held company called NeuroPace was founded in Mountain View, California to treat epilepsy by using responsive… Read More

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First FinFETs Manufactured at #50DAC!

First FinFETs Manufactured at #50DAC!
by Daniel Nenni on 06-09-2013 at 5:00 pm
Categories: EDA, Events, Sage DA, Solido, Synopsys


This was my 30[SUP]th[/SUP] DAC and the second most memorable. The most memorable was my second DAC (1985) in Las Vegas with my new bride. We had a romantic evening ending with ice cream sundaes at midnight that we still talk about. This year SemiWiki had Dr. Paul McLellan, Dr. Eric Esteve, Daniel Payne, Don Dingee, Randy Smith, and… Read More

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Metastability and Fatal System Errors

Metastability and Fatal System Errors
by Daniel Nenni on 06-09-2013 at 3:00 pm
Categories: EDA

Metastability is an inescapable phenomenon in digital electronic systems. This phenomenon has been known to cause fatal system errors for half a century. Over the years, designers have used convenient rules of thumb for designing synchronizers to mitigate it. However, as digital circuits have become more complex, smaller … Read More

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DAC IP Workshop: Are You Ready For Quality Control?

DAC IP Workshop: Are You Ready For Quality Control?
by Paul McLellan on 06-07-2013 at 3:08 am
Categories: EDA

On Sunday I attended an IP workshop which was presented by TSMC, Atrenta, Sonics and IPextreme. It turns out that the leitmotiv of the afternoon was SpyGlass.

Dan Kochpatcharin of TSMC was first up and gave a little bit of history of the company. They built up their capacity over the years, as I’ve written about before, and last… Read More