SILVACO 073125 Webinar 800x100
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EDA

Electronic Design Automation

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Synopsys Revamps Formal at #51DAC

Synopsys Revamps Formal at #51DAC
by Paul McLellan on 06-30-2014 at 6:02 pm
Categories: EDA, Synopsys

Synopsys announced verification compiler a couple of months ago and dropped hints about their static and formal verification. They haven’t announced anything much for a couple of years and it turns out that the reason was that they decided that the technology that they had, some internally developed and some acquired, … Read More

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Virtual Prototype Update from #51DAC

Virtual Prototype Update from #51DAC
by Daniel Payne on 06-30-2014 at 12:07 pm
Categories: EDA

EDA industry pundit Gary Smithhas been talking about the electronics industry adopting an ESL tool flow for decades, so it was my pleasure to speak with Bill Neifertof Carbon Design Systemsat DAC this month because his company has been offering both tools and models that enable a virtual prototyping design flow.… Read More

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What can you do when your fab closes down?

What can you do when your fab closes down?
by Daniel Nenni on 06-29-2014 at 4:00 pm
Categories: EDA

A recent report from IC Insights described 72 wafer fabs that have closed in the past five years. Eight more plants have gone in 2014, showing the trend is continuing.

This leaves their customers with a problem: what can they do when the fab shuts down? Some may recognise that their own technology has reached the end of its life and work… Read More

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High Level Synthesis update from #51DAC

High Level Synthesis update from #51DAC
by Daniel Payne on 06-27-2014 at 8:00 pm
Categories: EDA

Every since Synopsys dominated the logic synthesis market in the 1980’s we’ve had something called HLS – High Level Synthesis, meaning something higher than what Design Compiler can understand as input. At DACthis year I met with Mark Milligan of Calypto to get an update on what’s new with HLS. I first… Read More

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Standard Cell, IO and Hard IP Validation update

Standard Cell, IO and Hard IP Validation update
by Daniel Payne on 06-27-2014 at 1:26 pm
Categories: EDA, Fractal Technologies

Every SoC team uses libraries of cells to get their new product to market quicker: Standard Cells, IO Cells and Hard IP blocks. One immediate question that comes to my mind is, “How clean are these cells?” Validating your cell libraries first makes sense, and will ensure that there are fewer surprises as your chip gets… Read More

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IP Management Update at DAC

IP Management Update at DAC
by Daniel Payne on 06-26-2014 at 12:42 pm
Categories: EDA, Perforce

To keep track of my business and personal finances I use software from Quicken, but for an SoC with hundreds of IP blocks how do you keep track of everything? The answer is found in the growing field of EDA tools for IP management, and at DACearlier this month I sat down with Neil Handof Methodics to get an update on what the industry trends… Read More

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What’s New with Circuit Simulation for Cadence?

What’s New with Circuit Simulation for Cadence?
by Daniel Payne on 06-26-2014 at 11:53 am
Categories: Cadence, EDA

Every year at DAC I enjoy making the rounds to see what’s new with SPICE circuit simulators, so on June 3rd I met with Xiuya Liand Dan Zhuof Cadence in San Francisco to get an update about their Spectre tool. There’s plenty of competition in the SPICE area from Mentor Graphics (Analog FastSPICE, Eldo, ADiT), Synopsys … Read More

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Real FPGAs don’t eat fake test vectors

Real FPGAs don’t eat fake test vectors
by Don Dingee on 06-26-2014 at 8:00 am
Categories: Aldec, EDA, FPGA

Vector blasting hardware is as old as digital test methodology itself. In the days of relatively simple combinational and finite state machine logic, a set of vectors aimed broadside at inputs could shake loose most faults with observable outputs. With FPGAs, creating an effective set of artificial test vectors has become a lot… Read More

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Single Event Upsets

Single Event Upsets
by admin on 06-25-2014 at 5:04 pm
Categories: EDA

Do you know what a SEE is? It stands for single event upset. We live on a radioactive planet which is also bombarded with cosmic rays, so particles are bombarding our chips. The materials used in packaging also can create particles that cause problems, even the solder. Reliability and aging has been an area that has not been at the forefront… Read More

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Wally Rhines at #51DAC: EDA Grows From Solving New Problems

Wally Rhines at #51DAC: EDA Grows From Solving New Problems
by Paul McLellan on 06-24-2014 at 8:23 pm
Categories: EDA, Siemens EDA

Wally Rhines gave the keynote at DAC in 2004. One of the things that he pointed out ten years ago was that EDA revenue for any given market segment is pretty much flat once the initial growth phase has taken place and the market has been established. Incremental EDA revenue only comes from delivering new capabilities. Historically… Read More