This will be a year of change for the fabless semiconductor ecosystem, absolutely. Last year we were wondering how Samsung Mobile was going to compete with the China clones and other low end smart phones. We now know the answer to that question thanks to the Chipworks tear down of the Galaxy S6. SemiWiki IP expert Dr. Eric Esteve blogged… Read More
Electronic Design Automation
Variation Alphabet Soup
On-chip variation (OCV) is a major issue in timing signoff, especially at low voltages or in 20/16/14nm processes. For example, the graph below shows a 20nm inverter. At 0.6V the inverter has a delay of 2 (nominalized) units. But due to on-chip variation this might be as low as 1.5 units or as high as 3 units, which is a difference from… Read More
DAC Keynotes: Mark Your Calendar
DAC starts in San Francisco on June 8th. The kickoff keynote at 9.20am that morning is by Brian Otis of Google. He is a director at Google[x]. According to Wikipedia:Google X, stylized as Google[x], is a semi-secret facility run by Google dedicated to making major technological advancements. It is located about a half mile from … Read More
ANSYS Event to Highlight Cutting Edge Technology Development
If you follow technology news, it would be hard to deny that we live in exciting times. In some ways there is an unparalleled amount of big and cool technology development going on right now. We all have followed the rise of Tesla Motors. They took over a long vacant US big-auto plant in Fremont and are reinventing the US automobile industry.… Read More
EDPS: Fins and FinFETs
Look at those dolphins with fins on their backs. Did you know that FinFETs are actually named after them since Chenming Hu and his team though that they looked like a fish’s fin? And since they invented FinFETs they got to name them too. But those dolphins also mean that it is nearly time for this years Electronic Design Process… Read More
What is Skipper?
What is Skipper? Well, it seems it’s a penguin in the movie Madagascar. And one of Barbie’s sisters. Who knew? But for Semiwiki readers it’s an integrated chip finishing platform from ICScape. Skipper can read in full-chip layout extremely fast, examine it and manipulate it in various ways, and write it out again.… Read More
Secret Sauce for Successful Mixed-signal SoCs
For a design engineer engulfed in the daily rigorous routine of having to keep in sync with updates from various design team members as well the dictums of the design management team, the task of remaining up-to-date with the design information is very often daunting.
What design changes have been checked in this week? Is the verification… Read More
Verifying the RTL Coming out of a High-Level Synthesis Tool
With High-Level Synthesis (HLS) the first benefit that comes to my mind is reduced design time, because coding with C or SystemC is more efficient than low-level RTL code. What I’ve just learned is that there’s another benefit, a reduction in the amount of functional simulation required. One HLS customer was able … Read More
The Earth is Not Flat; Neither is IP
Chip design is largely about assembling pre-designed IP, either developed in other groups in the same company, or brought in from a 3rd party, or occasionally developed within the SoC design group itself. But that makes it sound like it is a bunch of blocks linked together with some interconnect, but of course another important … Read More
CEVA Eyes DSP Scale in China’s $65 LTE Handsets
China Mobile’s bid to go for 3-mode Long-Term Evolution (LTE) has led to the first major breakthrough, $65 LTE handsets, and here baseband and application processors provided by chipmakers like Leadcore Technology, MediaTek and Spreadtrum Communications have all one thing in common: DSP cores from CEVA Inc.
The advent… Read More


Semidynamics Unveils 3nm AI Inference Silicon and Full-Stack Systems