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All Models Are Wrong, Some Are Useful

All Models Are Wrong, Some Are Useful
by Paul McLellan on 09-15-2015 at 7:00 am

“All models are wrong, some are useful.” This remark is attributed to the statistician George Box who used it as the section heading in a paper published in 1976.

Just for fun I looked up a few semiconductor statistics from 1976. Total capital spending was $238M in Japan and $306M in US and…that’s it, there was nobody else back then … Read More


Mongoose: The Making of Samsung’s Custom CPU Core

Mongoose: The Making of Samsung’s Custom CPU Core
by Majeed Ahmad on 09-14-2015 at 4:00 pm

Samsung is seemingly ready to move to a new milestone in its brief but exciting system-on-chip (SoC) history: a custom CPU core codenamed Mongoose. It’s going to be based on ARMv8 instruction set and is expected to outperform the Exynos 7420 application processor that Samsung unveiled this year. There are some media reports… Read More


Thermal Reliability and Power Integrity for IC Design

Thermal Reliability and Power Integrity for IC Design
by Daniel Payne on 09-14-2015 at 12:00 pm

When I designed DRAM chips at Intel back in the 1970’s we didn’t really know what the die temperature would be before taping out silicon, instead we waited for packaged parts to come back and then did our thermal measurements. IC designers today don’t have that luxury of taping out their new SoC without having … Read More


Replacing the British Museum Algorithm

Replacing the British Museum Algorithm
by Paul McLellan on 09-14-2015 at 7:00 am

In principle, one way to address variation is to do simulations at lots of PVT corners. In practice, most of this simulation is wasted since it adds no new information, and even so, important corners will get missed. This is what Sifuei Ku of Microsemi calls the British Museum Algorithm. You walk everywhere. And if you don’t walk to… Read More


Moving up Verification to Scenario Driven Methodology

Moving up Verification to Scenario Driven Methodology
by Pawan Fangaria on 09-11-2015 at 12:00 pm

Verification complexity and volume has always been on the rise, taking significant amount of time, human, and compute resources. There are multiple techniques such as simulation, emulation, FPGA prototyping, formal verification, post-silicon testing, and so on which gain prominence in different situations and at different… Read More


What’s the Difference between Emulation and Prototyping?

What’s the Difference between Emulation and Prototyping?
by Tom Dillinger on 09-10-2015 at 12:00 pm

Increasing system complexity requires constant focus on the optimal verification methodology. Verification environments incorporate a mix of: transaction-based stimulus and response monitors, (pseudo-)random testcase generation, and ultimately, system firmware and software. RTL statement and assertion coverage… Read More


Explore Your Interconnect the ICScape Way

Explore Your Interconnect the ICScape Way
by Paul McLellan on 09-09-2015 at 7:00 am

One of the surprises at DAC for ICScape was to be listed on Gary Smith’s list of companies to see. Surprised, since ICScape had never presented their products to him. They were listed under design debug. They don’t have a single product that really falls under that description, but rather a family of tools under the ICExplorer… Read More


Congratulations Dr. Walden C. Rhines!

Congratulations Dr. Walden C. Rhines!
by Daniel Nenni on 09-08-2015 at 1:00 pm

A funny thing happened at the Design Automation Conference last June in San Francisco. I was browsing the Kaufman award winner mug shots in the EDAC booth and noticed that Wally Rhines was NOT a winner. You can see them HERE. Immediately in disbelief I said to myself: Self, how can this be? Joe Costello, Aart de Geus, and some other guys… Read More


How MunEDA Helps Solve the Difficulties of AMS/RF IP Reuse

How MunEDA Helps Solve the Difficulties of AMS/RF IP Reuse
by Tom Simon on 09-08-2015 at 12:00 pm

Reusing design IP is crucial for competitiveness. The need for reuse occurs with new designs on the same process node as the original design, new designs at the same node but using a different PDK or foundry, or designs on a different process node – usually smaller. However, achieving effective IP reuse has always been a challenge.… Read More


M&A Frenzy in the Chip Industry, the Growth of GaN, and Why It Matters

M&A Frenzy in the Chip Industry, the Growth of GaN, and Why It Matters
by Alex Lidow on 09-07-2015 at 12:00 pm

If expanding industries typically indicate vibrancy, a race to acquire and consolidate is generally reflective of the opposite – a period of slowed growth in mature, once high-flying categories. And while many industries experience a period of stardom, followed by a sharp and steady decline, we should be extremely worried whenRead More