With the advent of SoCs, design abstractions and verification has moved up at the system level. It’s imperative that EDA moves up the value chain to start design automation at system level. The System Design Automation will be the new face of EDA in coming years.… Read More
Electronic Design Automation
Why NXP is Moving to FD-SOI (Part II)
At NXP, we’re very excited about the prospects for our new i.MX 7 and 8 series of applications processors, which we’re manufacturing on 28nm FD-SOI. As noted in part I of this article series, the new i.MX 7 series, which leverages the 32-bit ARM v7-A core, is targeting the general embedded, e-reader, medical, wearable… Read More
TSMC and Solido on Variation-Aware Design of Memory and Standard Cell at Advanced Process Nodes
Being that TSMC and Solido are founding members of SemiWiki, you should be able find out everything you ever wanted to know on their respective landing pages. If not, just ask a question in the SemiWiki forum and I can assure you it will be answered in great detail. And here are some other interesting 2015 factoids from Solido:… Read More
Why is NXP Moving to FD-SOI?
The latest generations of power efficient and full-featured applications processors in NXP’s very successful and broadly deployed i.MX platform are being manufactured on 28nm FD-SOI. The new i.MX 7 series leverages the 32-bit ARM v7-A core, targeting the general embedded, e-reader, medical, wearable and IoT markets, where… Read More
One FPGA synthesis flow for different IP types
Both Altera and Xilinx are innovative companies with robust ecosystems, right? It would be a terrible shame if you located the perfect FPGA IP block for a design, but couldn’t use it because it was in the “wrong” format for your preferred FPGA. What if there were a way around that?
There is a compelling argument to use each FPGA vendor’s… Read More
Seven Reasons to Attend DAC in Austin
I’m attending the 53rd Design Automation Conference (DAC) in Austin, Texas starting June 5th, and there are at least seven reasons that you should consider attending as well. For decades now DAC has been the premier place for all the players in our semiconductor ecosystem to get together: Academics, Commercial vendors … Read More
Are Standard Cell Libs, Memories and Mixed-signal IP Availabe at 7nm FF?
More than 500 designers (562) have responded to a survey made in 2015 by Synopsys. Answering to the question “What is the fastest clock speed of your design?” 56% have mentioned a clock higher than 500 MHz (and still 40% higher than 1 GHz). If you compare with the results obtained 10 years ago, the largest proportion of answers was for… Read More
Eight Improvements for PCB Software
I first met John Durbetaki at Intel in Aloha, Oregon and we both had a keen interest in the nascent personal computer industry. My first PC was made by Radio Shack and dubbed the TRS-80 which maxed out at 48KB of RAM. I kept watch on Durbetaki as he left Intel and formed his own company OrCAD in 1985 to serve the needs of PC-based CAD software.… Read More
Cadence loads up on MACs for vision with CNNs
For vision DSP IP running convolutional neural networks (CNNs), a big driver of performance is increasing the bits processed per cycle with parallel MACs. Tom Simon did a great job in recent posts of introducing CNNs at a high level, so I’ll look at what is architecturally behind Cadence’s latest announcement: the Tensilica Vision… Read More
How to Deal With Seven Design Closure Issues
The challenge of tracking design progress is a shared problem for individual designers, team leaders, and project managers. At each level the ability to step back from just reviewing error log files and seeing the arc of the whole design as it moves forward is valuable. The difficulty of seeing the whole picture is exacerbated when… Read More
Intel: Pushing EMIB Forward: Design Methodology Insights with Synopsys Tools