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EDA

Electronic Design Automation

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The Mechanical Reliability of IC Packages

The Mechanical Reliability of IC Packages
by Daniel Payne on 01-31-2016 at 12:00 pm
Categories: Dassault Systemes, EDA

At Intel back in the late 1970’s we were designing DRAM chips and mounting them in ceramic and plastic packages, however there were problems when some of the die would crack inside of the package because of thermal mismatch issues with how the die was attached to the heat spreader inside the package. Back then we really didn’t… Read More

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5nm Chips? Yes, but When?

5nm Chips? Yes, but When?
by Pawan Fangaria on 01-31-2016 at 7:00 am
Categories: Automotive, EDA, FD-SOI, Foundries, FPGA, IoT, Mobile

For any invention, technical proof of concept or prototyping happens years ahead of the invention being infused into actual products. When we talk about 5nm chip manufacturing, a test chip was already prototyped in last October, thanks to Cadence and Imec. Details about this chip can be found in a blog at Semiwiki (link is given … Read More

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Domain Crossing Verification Needs Continue to Grow

Domain Crossing Verification Needs Continue to Grow
by Bernard Murphy on 01-29-2016 at 4:00 pm
Categories: EDA, Synopsys

Clock domain crossing (CDC) analysis has been around for many years, initially as special checks in verification or static timing analysis, but it fairly quickly diverged into specialized tools focused just on this problem. CDC checks are important because (a) you can lose data or even lock up at, or downstream of a poorly-handled… Read More

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Evaluating the Performance of Design Data Management Software

Evaluating the Performance of Design Data Management Software
by Karim Khalfan on 01-29-2016 at 12:00 pm
Categories: Cliosoft, EDA

In the wake of increased global competitiveness and shorter time-to-market windows, there has been a renewed focus by design management on the underlying data management infrastructure of the design teams. An increasing number of systems-on-chip (SoCs) now have some type of analog, digital and/or RF modules, making it imperative… Read More

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The Fine Art of Engineering

The Fine Art of Engineering
by Nazita Saye on 01-28-2016 at 12:00 pm
Categories: EDA, Events

There’s a small art gallery near the office. It features a new set of paintings by a local artist every two weeks. As I walk by I tend to check out what’s hanging in there. Sometimes I turn up my nose at what I see – a bit too wacky, a bit too abstract, a bit too paint by numbers. Sometimes I walk in to take a closer look but leave the shop empty-handed… Read More

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True Random Number Generation

True Random Number Generation
by Bernard Murphy on 01-27-2016 at 4:00 pm
Categories: IP, Synopsys

Random numbers are central to modern security systems. The humble password, perhaps the least profound application, is encrypted and verified against using SHA or MD algorithms with a random number salt. You probably remember a college class on how to generate pseudo-random numbers algorithmically, some very sophisticated.… Read More

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Does IoT need Sensor Fusion? Yes, but at low-power, low cost…and higher performance

Does IoT need Sensor Fusion? Yes, but at low-power, low cost…and higher performance
by Eric Esteve on 01-27-2016 at 12:00 pm
Categories: IP, Synopsys

We said this in the past, but let’s reiterate that IoT devices will be successful if they can meet low-cost and low-power requirements. Low-cost is the condition for IoT devices market penetration, I mean such a market adoption that we count several IoT systems (and dozens of devices) in every house. That’s the only way to reach the… Read More

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In Low Voltage Timing, the Center Cannot Hold

In Low Voltage Timing, the Center Cannot Hold
by Bernard Murphy on 01-25-2016 at 7:00 am
Categories: CLK Design Automation, EDA

When I started discussing this topic with Isadore Katz, I was struggling to find a simple way to explain what he was telling me – that delay and variance calculations in STA tools are wrong at low voltage because the average (the center) of a timing distribution shifts from where you think it is going to be. He told me that I’m not alone… Read More

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The Death of Moore’s Law

The Death of Moore’s Law
by Michael Barger on 01-22-2016 at 12:00 pm
Categories: EDA

For the last several years, people have predicted the end of Moore’s Law. The reasoning is that there is a limit at which one can’t shrink transistors any further. A reoccurring comment has been “You can’t divide an atom.” I had assumed that its demise would be at the hands of a new paradigm like quantum computing. Now, with Intel’s … Read More

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When Good Standards Get Lost – the UVM Register Model

When Good Standards Get Lost – the UVM Register Model
by Bernard Murphy on 01-20-2016 at 12:00 pm
Categories: EDA, Siemens EDA

Some time ago I wrote a DeepChip viewpoint on DVCON 2014 in which I praised a Mentor paper “Of Camels and Committees”. The authors argued that while the UVM standards committee had a done a great job in the early releases, the 1.2 release was overloaded with nice-to-have features with questionable value for a standard, particularly… Read More