Banner Electrical Verification The invisible bottleneck in IC design updated 1
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EDA

Electronic Design Automation

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Who protects power protection chips?

Who protects power protection chips?
by Tom Simon on 05-25-2016 at 12:00 pm
Categories: EDA, Magwel

Power protection chips are widely used these days to protect sensitive circuitry from over-voltage and over-current stress. However, these workhorse chips are often subjected to extraordinary thermal stress themselves and need to be protected from burning up – literally.

Power protection chips work like electronic fuses,… Read More

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Testing IGBTs before they go into EVs

Testing IGBTs before they go into EVs
by Don Dingee on 05-23-2016 at 4:00 pm
Categories: Automotive, EDA, Siemens EDA

In the pages of SemiWiki, we are usually talking about what to do with billions of really small transistors – for a change of pace today, we’ll discuss what to do with a few really big ones. Mentor Graphics has just announced their latest MicReD platform for thermal testing of IGBTs, experiencing a resurgence (pun intended) thanks… Read More

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What Does an MPW and a Pizza Have in Common?

What Does an MPW and a Pizza Have in Common?
by Daniel Nenni on 05-23-2016 at 12:00 pm
Categories: EDA, eSilicon, Semiconductor Services, TSMC

Design starts are critical to the growth of the semiconductor industry so enabling them is a common theme on SemiWiki. One thing we have not covered in detail is multi-project wafer services (MPW) which is the equivalent of ride sharing through the initial mask and wafer process. Larger semiconductor companies already do this … Read More

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"Re-Inventing" Tapeout Sign-off — Applying Big Data Techniques to Electrical Analysis

"Re-Inventing" Tapeout Sign-off — Applying Big Data Techniques to Electrical Analysis
by Tom Dillinger on 05-23-2016 at 7:00 am
Categories: Ansys, Inc., EDA

A common SoC design methodology in current use starts with preparation of the physical floorplan — e.g., block/pin placement, global clock domain and bus signal planning, developing the global/local power distribution (and dynamic power domain management techniques). Decoupling capacitor estimated densities and… Read More

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Rebooting EDA

Rebooting EDA
by Bernard Murphy on 05-23-2016 at 7:00 am
Categories: Ansys, Inc., EDA

In the 35 years since commercial EDA went mainstream a lot of advances have been made but the fundamental architecture and even the philosophy of tooling have really not advanced at all. Tools are designed around individual tasks – analysis and optimization within a specific domain – under the assumption that variability within… Read More

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Google TPU Another Step in a Shifting Semiconductor Landscape

Google TPU Another Step in a Shifting Semiconductor Landscape
by Bernard Murphy on 05-22-2016 at 4:00 pm
Categories: EDA

Markets work when consumers of a widget don’t feel there is significant differentiated value in making their own and would rather get lowest possible cost from experienced widget makers who can amortize their investment over high-volume sales to many customers. But that changes when a large consumer finds they can increase differentiated… Read More

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Where are the Entrepreneurs?

Where are the Entrepreneurs?
by Randy Smith on 05-22-2016 at 10:00 am
Categories: EDA, IoT, IP, Mobile

This week I attended the UpWest Labs event in San Francisco. UpWest Labs provides seed funding and incubation for a wide range of domains including Enterprise Software, Internet of Things, Infrastructure Technologies, Artificial Intelligence, Consumer Applications, Drones, Cyber Security, Augmented Reality / Virtual … Read More

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Aldec extends FPGA and ASIC flows at DAC

Aldec extends FPGA and ASIC flows at DAC
by Don Dingee on 05-20-2016 at 4:00 pm
Categories: Aldec, EDA

Aldec tools and services have long been associated with FPGA designs. As FPGAs have evolved toward more RTL-based designs, the similarities between a modern FPGA verification flow and an ASIC verification flow often leave them looking virtually the same. … Read More

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Stop FinFET Design Variation @ #53DAC and get a free book!

Stop FinFET Design Variation @ #53DAC and get a free book!
by Daniel Nenni on 05-20-2016 at 7:00 am
Categories: EDA, FinFET, Solido

If you plan on visiting Solido (the world leader in EDA software for variation-aware design of integrated circuits) at the Design Automation Conference next month for a demonstration of Variation Designer, register online now and get an autographed copy of “Mobile Unleashed”. Such a deal!

Solido Variation Designer is used by… Read More

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Bulking Up of Design Data Calls for Version Control on Steroids

Bulking Up of Design Data Calls for Version Control on Steroids
by Tom Simon on 05-17-2016 at 4:00 pm
Categories: EDA, Perforce

Even though design management systems are gaining popularity as a way to manage design data growth, they actually contribute to the problem of exploding data size. What we already know is that a linear increase in die size causes exponential growth in chip area, and that smaller feature sizes compound this effect in the same way.… Read More