Banner Electrical Verification The invisible bottleneck in IC design updated 1
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EDA

Electronic Design Automation

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Organizing Data is First Step in Managing AMS Designs

Organizing Data is First Step in Managing AMS Designs
by Don Dingee on 09-14-2016 at 4:00 pm
Categories: Cliosoft, EDA

Efficient collaboration is essential to meeting tight chip design schedules. In analog and mixed signal (AMS) design, collaboration has many facets. Design tools are usually specific to roles, and handoffs are numerous, especially when moving a design to a foundry. … Read More

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Mentor Functional Verification Study 2016

Mentor Functional Verification Study 2016
by Bernard Murphy on 09-14-2016 at 7:00 am
Categories: EDA, FPGA, Siemens EDA

Periodically, Mentor commissions a user/usage survey on Functional Verification, conducted by the Wilson Research Group, then they publish the results to all of us, an act of industry good-citizenship for which I think we owe them a round of thanks. Harry Foster at Mentor is breaking down the report into a series of 15 blogs. He’s… Read More

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Requirements Management and IP Management Working Together

Requirements Management and IP Management Working Together
by Daniel Payne on 09-12-2016 at 12:00 pm
Categories: EDA, Perforce

I first heard about requirements management back in 1995 while marketing a graphic HDL entry tool for an EDA vendor, and it sounded like a very useful automation approach, however our team quickly discovered that there were too many different vendors for requirements management, so there could be no simple way to integrate with… Read More

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A Powerful Case for the ARC SEM Processor

A Powerful Case for the ARC SEM Processor
by Bernard Murphy on 09-12-2016 at 8:06 am
Categories: IoT, Mobile, Security, Synopsys

Building devices for the IoT has become especially challenging thanks to two conflicting requirements. The device has to be small and ultra-low power in most applications but also in many of those applications it has to provide a high-level of security, especially to defend high-value targets like smart metering, payment terminals,… Read More

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TSMC and Solido to Share Experiences with Managing Variation in Webinar

TSMC and Solido to Share Experiences with Managing Variation in Webinar
by Tom Simon on 09-10-2016 at 7:00 am
Categories: EDA, Foundries, Solido, Synopsys, TSMC

TSMC knows better than anyone the effect that variation can have at advanced process nodes. Particularly in memory designs and in standard cell designs, variation has become a very critical because of its effects on yield and because of the high-cost of compensating for it. Smaller feature sizes combined with lower voltage thresholds… Read More

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Power-Aware Debug to Find Low-Power Simulation Bugs

Power-Aware Debug to Find Low-Power Simulation Bugs
by Daniel Payne on 09-09-2016 at 12:00 pm
Categories: EDA, Mobile, Synopsys

When I worked at Intel designing custom chips my management would often ask me, “Will first silicon work?” My typical response was, “Yes, but only for the functions that we could afford to simulate before tape-out.” This snarky response would always cause a look of alarm, quickly followed by a second … Read More

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Checkout the Upcoming Synopsys Power Webinar

Checkout the Upcoming Synopsys Power Webinar
by Bernard Murphy on 09-09-2016 at 7:00 am
Categories: EDA, Synopsys

This is part 3 of a series of 4 on low power design, scheduled for September 21st at 10am. Kiran Vittal and Ken Mason will be discussing using the SpyGlass Power solutions (analysis and verification) to optimize power at RTL. Atrenta always had a leading position in this area; I expect a year following their acquisition by Synopsys,… Read More

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Synopsys Webinar: MIPI Adoption Beyond Mobile, it’s now!

Synopsys Webinar: MIPI Adoption Beyond Mobile, it’s now!
by Eric Esteve on 09-04-2016 at 8:00 pm
Categories: Automotive, IoT, Mobile, Synopsys

Some of the various MIPI specifications are now massively used in mobile (smartphone or tablet), especially the Multimedia related specs like Camera Serial Interface (CSI-2), Display Serial Interface (DSI) and D-PHY. You have to implement with CSI-2 or DSI controller a serial based physical interface, D-PHY specified up to… Read More

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Pseudo random generator tutorial in VHDL (Part 3/3)

Pseudo random generator tutorial in VHDL (Part 3/3)
by Claudio Avi Chami on 09-04-2016 at 4:00 pm
Categories: EDA, FPGA



On the first two chapters of this Tutorial we started with a simple LFSR module and added a test bench. Then, on chapters three and four we upgraded our module with some features and learned to export the test bench data to files.
… Read More