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CEO Interview: Simon Butler of Methodics

CEO Interview: Simon Butler of Methodics
by Daniel Nenni on 10-24-2016 at 7:00 am

It has been interesting to watch Methodics transform from an EDA company with their VersIC design management product to Life Cycle Management with ProjectIC, and now a Systems Company with WarpStor. Methodics was founded in 2006 by 2 ex-Cadence experts in the Custom IC design tools space, Simon Butler and Fergus Slorach. Today… Read More


Fabless Photonic Design Flow Takes Shape as Cadence teams up with Lumerical and PhoeniX

Fabless Photonic Design Flow Takes Shape as Cadence teams up with Lumerical and PhoeniX
by Mitch Heins on 10-21-2016 at 4:00 pm

This week Cadence Design, Lumerical Solutions and PhoeniX Software hosted a two-day photonic summit and workshop. The first day had nearly 100 registered participants and featured industry leaders from Global Foundries, UCSB, MIT, Hewlett Packard Enterprise, General Electric, Boeing, Rockley Photonics, and Juniper Networks… Read More


Webinar Offers View into TSMC IP Design Methodology

Webinar Offers View into TSMC IP Design Methodology
by Tom Simon on 10-21-2016 at 12:00 pm

Standard cell and memory IP are key enablers for new process node availability. These two items must be in place early and be completely ready for a process node to scale to volume. Development of both leaves no room for error and they require the highest performance possible. Foundries are extremely focused on this and spend a lot… Read More


The Fabless Empire Strikes Back, Global Foundries and Cadence make moves into Integrated Photonics!

The Fabless Empire Strikes Back, Global Foundries and Cadence make moves into Integrated Photonics!
by Mitch Heins on 10-20-2016 at 4:00 pm

In August I wrote an article proclaiming Score 1 for IDMs vs Fabless and discussedIntel’sannouncement of volume production of their 100G PSM4 and 100G CWDM4 transceiver products.

This week the Fabless Empire strikes back.
Daniel Nenni and I attended a two-day Photonic Summit and workshop hosted by Cadence Design, PhoeniX Software
Read More


Why Integrate Bluetooth LE IP in a Single Wearable SoC?

Why Integrate Bluetooth LE IP in a Single Wearable SoC?
by Eric Esteve on 10-20-2016 at 12:00 pm

Did you know that, in over 800 teardowns of mobile and wearable products from 2012 to 2015, wireless chips outnumbered the actual number of products, indicating multiple wireless ICs in some designs ([SUP]1[/SUP])? It could be interesting to look at the advantages of integrating wireless technology such as Bluetooth low energy… Read More


ARM and SoftBank: A Joint Vision of the Future!

ARM and SoftBank: A Joint Vision of the Future!
by Daniel Nenni on 10-18-2016 at 8:00 pm

Next week is ARM TechCon and I’m extra excited about this one because of the SoftBank acquisition. In fact, the opening keynote says it all. ARM CEO Simon Segar and SoftBank CEO Masayoshi Son will discuss the next chapter in the book of ARM. To better prepare for this keynote you should probably read our book “Mobile Unleashed: The Read More


Achieving Lower Power through RTL Design Restructuring (webinar)

Achieving Lower Power through RTL Design Restructuring (webinar)
by Daniel Payne on 10-18-2016 at 4:00 pm

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From a consumer viewpoint I want the longest battery life from my electronic devices: iPad tablet, Galaxy Note 4 smart phone, Garmin Edge 820 bike computer, and Amazon Kindle book reader. In September I blogged about RTL Design Restructuring and how it could help achieve lower power, and this month I’m looking forward to … Read More


Circuit Simulation Videos Show How To

Circuit Simulation Videos Show How To
by Daniel Payne on 10-13-2016 at 4:00 pm

One of the things that I miss most about attending trade shows like DAC in the old days was that you actually got to see EDA tools being demonstrated live in the exhibit area. You could see what the GUI looked like, how the dialogs worked, and learn what kind of control you could have during analysis. Most of what you see today at DAC in the… Read More


Machine Learning – Turning Up the Sizzle in EDA

Machine Learning – Turning Up the Sizzle in EDA
by Bernard Murphy on 10-13-2016 at 7:00 am

There’s always a lot of activity in EDA to innovate and refine specialized algorithms in functional modeling, implementation, verification and many other aspects of design automation. But when Google, Facebook, Amazon, IBM and Microsoft are pushing AI, deep learning, Big Data and cloud technologies, it can be hard not to see… Read More


Case study illustrates 171x speed up using SCE-MI

Case study illustrates 171x speed up using SCE-MI
by Don Dingee on 10-12-2016 at 4:00 pm

As SoC design size and complexity increases, simulation alone falls farther and farther behind, even with massive cloud farms of compute resources. Hardware acceleration of simulation is becoming a must-have for many teams, but means more than just providing emulation… Read More