BroncoAI DVCon100x800 FIX
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Emulation Evaluation for the Ages!

Emulation Evaluation for the Ages!
by Daniel Nenni on 12-24-2018 at 7:00 am

One of the more entertaining things I get to observe in the semiconductor ecosystem is competitive customer evaluations of tools and IP. Seriously, this is where the rubber meets the road no matter what the press releases say.

This time it was emulators which is one of the most interesting EDA market segments since there is no dominant… Read More


Synopsys Offers Smooth Sailing for OTP NVM

Synopsys Offers Smooth Sailing for OTP NVM
by Tom Simon on 12-20-2018 at 12:00 pm

Nobody likes drama. Wait, let me narrow that down a bit. Chip designers really hate drama. They live in a world of risk and uncertainty, a world that tool and IP vendors spend considerable resources trying to make safer and more rational. It’s notable just how ironic that Sidense and Kilopass were duking out patent litigation in the… Read More


SoC Design Partitioning to Save Time and Avoid Mistakes

SoC Design Partitioning to Save Time and Avoid Mistakes
by Daniel Payne on 12-18-2018 at 12:00 pm

I started designing ICs in 1978 and continued through 1986, and each chip used hierarchy and partitioning but our methodology was totally ad-hoc, and documented on paper, so it was time consuming to make revisions to the chip or train someone else on the history or our chip, let alone re-use any portion of our chips again. Those old,… Read More


Cadence Automotive Summit Sensor Enablement Highlights

Cadence Automotive Summit Sensor Enablement Highlights
by Camille Kokozaki on 12-18-2018 at 7:00 am

At the November 14 Cadence Automotive Summit, Ian Dennison, Senior Group Director, outlined sensor enablement technologies and SoC mixed-signal design solutions, from Virtuoso electrically aware design with high current, high reliability, yield and performance tools and methodologies enabling ADAS/AV sensors for vehicle… Read More


Photonics with CurvyCore

Photonics with CurvyCore
by Alex Tan on 12-17-2018 at 12:00 pm

As a preferred carrier to data or energy, photonics technology is becoming broad and diverse. In IC design, silicon-photonics technology has been the enabler of new capabilities and has revolutionized many applications as Moore’s-based scaling started to experience a slowdown. It acts as new on-chip inductor in HPC design … Read More


Next-Generation Formal Verification

Next-Generation Formal Verification
by Daniel Nenni on 12-14-2018 at 12:00 pm

As SoC and IP designs continue to increase in complexity while schedules accelerate, verification teams are looking for methodologies to improve design confidence more quickly. Formal verification techniques provide one route to improved design confidence, and the increase in papers and interest at industry conferences… Read More


Sequential Equivalency Checks in HLS

Sequential Equivalency Checks in HLS
by Alex Tan on 12-13-2018 at 12:00 pm

Higher level synthesis (HLS) of an IP block involves taking its high-level design specification –usually captured in SystemC or C++, synthesizes and generates its RTL equivalent. HLS provides a faster convergence path to design code stability, promotes design reuse and lowers front-end design inception cost.

HLS and MentorRead More


Big Data Analytics in Early Power Planning

Big Data Analytics in Early Power Planning
by Bernard Murphy on 12-13-2018 at 7:00 am

ANSYS recently hosted a webinar talking about how they used the big-data analytics available in RedHawk-SC to do early power grid planning with static analytics, providing better coverage than would have been possible through pure simulation-based approaches. The paradox here is that late-stage analysis of voltage drops … Read More


DVCon is coming in February, now is the time to register early

DVCon is coming in February, now is the time to register early
by Daniel Payne on 12-12-2018 at 7:00 am

As 2018 wraps up this month it’s time to start thinking and planning for 2019, and if you work in the Silicon Valley then you’ll want to consider adding the 31st annual DVCon event planned for February 25-28 in San Jose. Surveys have shown for some time now that verification tasks actually take up more time on a SoC project… Read More


Imperas and RISC-V

Imperas and RISC-V
by Bernard Murphy on 12-06-2018 at 7:00 am

I met Imperas at TechCon this year because I wanted to become a bit more knowledgeable about virtual modeling. That led me to become more interested in RISC-V and a talk given by Krste Asanovic of UCB and SiFive. My takeaway surprised me. I had thought this was an open-source David versus proprietary Goliaths (Intel and ARM) battle… Read More