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I Thought that Lint Was a Solved Problem

I Thought that Lint Was a Solved Problem
by Daniel Nenni on 11-16-2018 at 12:00 pm

A few months back, we interviewed Cristian Amitroaie, the CEO of AMIQ EDA. We talked mostly about their Design and Verification Tools (DVT) Eclipse Integrated Development Environment (IDE) and how it helps design and verification engineers develop code in SystemVerilog and several other languages. Cristian also mentioned… Read More


Eliminate PCB Re Spins using an Integrated Multi Dimensional Verification Platform

Eliminate PCB Re Spins using an Integrated Multi Dimensional Verification Platform
by Daniel Nenni on 11-15-2018 at 12:00 pm

The rapidly increasing complexity of today’s designs, combined with schedule pressure to deliver innovative products to market as quickly as possible, strains engineering resources to the limit, often to the point of breaking. As a result, 17% of all projects get canceled, and another 28% miss their target release date (Source:… Read More


Mentor’s Symphony in Tune with AMS Designer Needs

Mentor’s Symphony in Tune with AMS Designer Needs
by Tom Simon on 11-14-2018 at 12:00 pm

Mixed signal simulation is a very hot topic these days. In modern designs, it is harder to draw a line between the analog and digital and work with them independently. Analog blocks are showing up everywhere. Even in what would have qualified as a digital design a few years ago, now designers need to look at things like PLLs, IOs and … Read More


Synopsys DDR5 LPDDR5 Memory Interface IP Targets AI, Automotive, and Mobile SoCs

Synopsys DDR5 LPDDR5 Memory Interface IP Targets AI, Automotive, and Mobile SoCs
by Camille Kokozaki on 11-14-2018 at 7:00 am

Synopsys announced on October 24 new DesignWare[SUP]®[/SUP] Memory Interface IP solutions supporting the next-generation DDR5 and LPDDR5 SDRAMs. The DDR5 and LPDDR5 IP significantly increase memory interface bandwidth compared to DDR4 and LPDDR4/4X SDRAM interfaces, while reducing area and improving power efficiency.… Read More


Fusion Synthesis for Advanced Process Nodes

Fusion Synthesis for Advanced Process Nodes
by Alex Tan on 11-13-2018 at 12:00 pm

Synopsys recently unleashed Fusion Compiler™, a new RTL-to-GDSII product that enables a data-driven design implementation by revamping Design Compiler architecture and leveraging the successful Fusion Technology –seamlessly fusing the logical and physical realms to produce predictable QoR. It is a long-awaited… Read More


DAC 2019 to Host the Second System Design Contest!

DAC 2019 to Host the Second System Design Contest!
by Daniel Nenni on 11-13-2018 at 7:00 am

Interested in showing off your talent in developing deep learning algorithms on embedded hardware platforms for solving real-world problems? Join the second System Design Contest (SDC) at the 56[SUP]th[/SUP] Design Automation Conference in 2019!… Read More


Webinar: NVIDIA Talks High Quality Metrics in Power Integrity Signoff

Webinar: NVIDIA Talks High Quality Metrics in Power Integrity Signoff
by Bernard Murphy on 11-09-2018 at 12:00 pm

There’s a familiar saying that you can’t improve what you can’t measure. Taking that one step further, the more improvement you want, the more accurately you have to measure. This become pretty important when you’re building huge designs in advanced technologies. Margins are a lot tighter all round and use-cases are massively… Read More


Coupled Electro-thermal Analysis Essential for PowerMOS Design

Coupled Electro-thermal Analysis Essential for PowerMOS Design
by Tom Simon on 11-08-2018 at 12:00 pm

Power device designers know that when they see a deceptively simple pair of PowerMOS device symbols in the output stage of a power converter circuit schematic, they are actually looking at a massively complex network of silicon and metal interconnect. The corresponding physical devices can have a total device W on the order of … Read More


Emulation from In Circuit to In Virtual

Emulation from In Circuit to In Virtual
by Bernard Murphy on 11-08-2018 at 7:00 am

At a superficial level, emulation in the hardware design world is just a way to run a simulation faster. The design to be tested runs on the emulator, connected to whatever test mechanisms you desire, and the whole setup can run many orders of magnitude faster than it could if the design was running inside a software simulator. And … Read More


Why Did Ambiq Micro Select HiFi-5 DSP IP for Next Generation MCU?

Why Did Ambiq Micro Select HiFi-5 DSP IP for Next Generation MCU?
by Eric Esteve on 11-06-2018 at 6:00 am

Ambiq Micro has built a family of voice processing MCU dedicated to battery powered, energy sensitive systems, supporting mobile application like wearable. The company is facing two strong challenges: support computationally intensive processing (NN-based far field) and speech recognition algorithms, while offering … Read More