Verification engineers are the unsung heroes making sure that our smart phone chips, smart watches and even smart cars function logically, without bugs or unintended behavior. Hidden bugs are important to uncover, but what approach is best suited for this challenge?
With the Universal Verification Methodology (UVM) there’s… Read More
Electronic Design Automation
Lip-Bu Keynote at CDNLive 2019
Cadence CEO Lip-Bu Tan is always an interesting guy to listen to for his broader technology industry overview and his insight into emerging tech through his Walden International investments. Though we’re usually heads-down in challenging technical problems, it’s good to look up from time to time to check whether what … Read More
IC Integrity Thesis
Most of my investments are associated with large changes in the semiconductor industry. These changes create opportunities for new and disruptive technologies. I also look to find solutions that provide a compelling reason to adopt a new technology or approach. When talking about a new approach, it often takes longer to overcome… Read More
IP-XACT The Answer for IP Reuse
To a lawyer, the term intellectual property means just about anything intangible that has value. However, when you bring that term up in the context of semiconductor design, it means something pretty specific to most people. Yet the implied meaning of the term intellectual property (IP) within the semiconductor field has changed… Read More
Cloud-based Functional Verification
The big three EDA vendors are constantly putting more of their tools in the cloud in order to speed up the design and verification process for chip designers, but how do engineering teams approach using the cloud for functional verification tests and regressions? At the recent Cadence user group meeting (CDNLive) there was a presentation… Read More
The Answer to Why Intel PMOS and NMOS Fins are Different Sizes
Like many others, we have often wondered why the PMOS fins on advanced microprocessors from Intel are narrower than the NMOS fins (6nm versus 8nm). This unusual dimensional difference first occurred at the 14nm node and it coincided with the introduction of Solid State Doping (SSD) of the fins at this node.
We have concluded that… Read More
My Thoughts on Cadence in the Cloud
The cloud is a highly popular term that a lot of people don’t fully understand. If you are one of those people please read on as I will share my experience, observations, and opinions. Even if you are a cloud aficionado you may want to catch up on what’s new with EDA cloud services so again read on.
When we first started SemiWiki 9 years … Read More
Solving the EM Solver Problem
The need for full wave EM solvers has been creeping into digital design for some time. Higher operating frequencies – like those found in 112G links, lower noise margins – caused by multi level signaling such as in PAM-4, and increasing design complexity – as seen in RDL structures, interposers, advanced connector… Read More
How to Spice Up Your Library Characterization
It used to be that at the mention of libraries, people would think of foundry PDK deliverables. However, now a host of factors such as automotive thermal requirements, nanometer FinFET processes, near threshold voltages, higher clock rates, high volumes, etc., have dramatically changed library development. These factors … Read More
With Great Power Comes Great Visuality
Every system-on-chip (SoC) designer worries about power. Many widely used electronics applications run on batteries, including smartphones, tablets, autonomous vehicles, and many Internet-of-Things (IoT) devices. Even “big iron” products such as network switches and compute servers must be careful when it comes to power… Read More


Weebit Nano Reports on 2025 Targets