If we look at the semiconductor industry expansion during the last 25 years, adoption of design IP in every application appears to be one of the major factors of success, with silicon technology incredible development by a x100 factor, from 250nm in 2018 to 3nm (if not 2nm) in 2023. We foresee the move to chiplet-based architecture… Read More
Unleashing the 1.6T Ecosystem: Alphawave Semi’s 200G Interconnect Technologies for Powering AI Data Infrastructure
In the rapidly evolving landscape of artificial intelligence (AI) and data-intensive applications, the demand for high-performance interconnect technologies has never been more critical. Even the 100G Interconnect is already not fast enough for infrastructure applications. AI applications, with their massive datasets… Read More
When Will Structured Assembly Cross the Chasm?
First, a quick definition. By “structured assembly,” I mean the collection of tools to support IP packaging with standardized interfaces, SoC integration based on those IPs together with bus fabric and other connectivity hookups, register definition and management in support of hardware/software interface definition, … Read More
UCIe InterOp Testchip Unleashes Growth of Open Chiplet Ecosystem
Intel recently made headlines when CEO Pat Gelsinger unveiled the world’s first UCIe interoperability test chip demo at Innovation 2023. The test chip built using advanced packaging technology is codenamed Pike Creek and is used to demonstrate interoperability across chiplets designed by Intel and Synopsys. More details … Read More
Prototyping Chiplets from the Desktop!
S2C has been successfully delivering rapid SoC prototyping solutions since 2003 with over 600 customers, including 6 of the world’s top 10 semiconductor companies. I personally have been involved with the prototyping market for a good part of my career and know S2C intimately.
S2C is the leading independent global supplier… Read More
Successful 3DIC design requires an integrated approach
While the leap from traditional SoC/IC designs to Three-Dimensional Integrated Circuits (3DICs) designs brings new benefits and opportunities, it also introduces new challenges. The benefits include performance, power efficiency, footprint reduction and cost savings. The challenges span design, verification, thermal… Read More
Ensuring 3D IC Semiconductor Reliability: Challenges and Solutions for Successful Integration
One of the most promising advancements in the semiconductor field is the development of 3D Integrated Circuits (3D ICs). 3D ICs enable companies to partition semiconductor designs and seamlessly integrate silicon Intellectual Property (IP) at the most suitable process nodes and processes. This strategic partitioning yields… Read More
Managing IP, Chiplets, and Design Data
Design re-use has enabled IC design teams to create billion-transistor designs where hundreds of IP blocks are pre-built from internal or external sources. Keeping track of where each of these IP blocks came from, what their version status is, managing IP, or even discerning their license status can be a full-time job if tracked… Read More
The Path to Chiplet Architecture
If you have anything to do with the semiconductor industry, you already know that one of the hottest areas for both manufacturing and EDA are systems designed with advanced packaging, basically putting more than one die (aka chiplets) in the same package.
When 3D packaging was first introduced, there were not really any effective… Read More
Synopsys Panel Updates on the State of Multi-Die Systems
Synopsys recently hosted a cross-industry panel on the state of multi-die systems which I found interesting not least for its relevance to the rapid acceleration in AI-centric hardware. More on that below. Panelists, all with significant roles in multi-die systems, were Shekhar Kapoor (Senior Director of Product Management,… Read More
Intel’s Pearl Harbor Moment