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Fabless Photonic Design Flow Takes Shape as Cadence teams up with Lumerical and PhoeniX

Fabless Photonic Design Flow Takes Shape as Cadence teams up with Lumerical and PhoeniX
by Mitch Heins on 10-21-2016 at 4:00 pm

This week Cadence Design, Lumerical Solutions and PhoeniX Software hosted a two-day photonic summit and workshop. The first day had nearly 100 registered participants and featured industry leaders from Global Foundries, UCSB, MIT, Hewlett Packard Enterprise, General Electric, Boeing, Rockley Photonics, and Juniper Networks… Read More


The Fabless Empire Strikes Back, Global Foundries and Cadence make moves into Integrated Photonics!

The Fabless Empire Strikes Back, Global Foundries and Cadence make moves into Integrated Photonics!
by Mitch Heins on 10-20-2016 at 4:00 pm

In August I wrote an article proclaiming Score 1 for IDMs vs Fabless and discussedIntel’sannouncement of volume production of their 100G PSM4 and 100G CWDM4 transceiver products.

This week the Fabless Empire strikes back.
Daniel Nenni and I attended a two-day Photonic Summit and workshop hosted by Cadence Design, PhoeniX Software
Read More


You’re Going to Want to Attend the Cadence Photonics Summit Workshop, October 19-20

You’re Going to Want to Attend the Cadence Photonics Summit Workshop, October 19-20
by Tom Dillinger on 10-05-2016 at 12:00 pm

Photonics IC’s (PIC’s) are used to transmit and receive data through a (single-mode or multi-mode) optical fiber carrier, and provide the requisite electro-optical conversion for system integration. The architecture of the PIC spans the full characteristics of data transmission and reception:

  • light generation

Typically,… Read More


"Rigid-Flex Design is Coming"

"Rigid-Flex Design is Coming"
by Tom Dillinger on 10-04-2016 at 12:00 pm

Printed circuit boards that incorporate a combination of traditional PCB technology with flexible substrates, aka rigid-flex designs, have enabled an increasing variety of product designs, that leverage the unique physical form factor and lightweight options that rigid-flex technology offers. Yet, this technology requires… Read More


Cadence DSPs float for efficiency in complex apps

Cadence DSPs float for efficiency in complex apps
by Don Dingee on 09-29-2016 at 4:00 pm

Floating-point computation has been a staple of mainframe, minicomputer, supercomputer, workstation, and PC platforms for decades. Almost all modern microprocessor IP supports the IEEE 754 floating-point standard. Embedded design, for reasons of power and area and thereby cost, often eschews floating-point hardware… Read More


Solutions for Variation Analysis at 16nm and Beyond

Solutions for Variation Analysis at 16nm and Beyond
by Tom Simon on 09-22-2016 at 7:00 am

Variation is still the tough nut to crack for advanced process nodes. The familiar refrain of lower operating voltages and higher performance requirements make process variation an extremely important design consideration. As far back as the early 2000’s design teams have been looking for a better approach to model variation… Read More


Next Book Signing: Linley Processor Conference 2016!

Next Book Signing: Linley Processor Conference 2016!
by Daniel Nenni on 09-20-2016 at 12:00 pm

It is a busy month for book signings but it is a pleasure to do it for the greater good of the semiconductor industry. It really is an honor to meet the people who keep our electronic devices on the leading edge of technology, absolutely.

The Linley Processor Conference is on September 27[SUP]th[/SUP]and 28[SUP]th[/SUP] at the Hyatt… Read More


Emulation as a Multi-User Shareable Resource

Emulation as a Multi-User Shareable Resource
by Bernard Murphy on 09-19-2016 at 7:00 am

One of the great advantages of emulation is that runtimes are much faster than for simulation – sufficiently fast that you can really debug hardware together with software for comprehensive use-case testing. A not so great aspect is that emulators are expensive and, until relatively recently, not particularly easy to share across… Read More


The Package Assembly Design Kit (PADK)… the start of something big

The Package Assembly Design Kit (PADK)… the start of something big
by Tom Dillinger on 08-19-2016 at 12:00 pm

Integrated wafer-level fanout (WLFO) packaging technology is emerging as a foundation for multi-die solutions. Mobile product applications require focus on both aggressive chip-to-chip interface performance, as well as the final package volume. Traditional multi-chip packages using PCB laminate substrates do not readily… Read More


Custom layout productivity requires unrelenting EDA vendor focus

Custom layout productivity requires unrelenting EDA vendor focus
by Tom Dillinger on 08-05-2016 at 12:00 pm

The EDA tools industry relies upon ongoing productivity enhancements to existing products, to manage increasing SoC complexity and to address shrinking design schedules. The source of ideas for enhancements can come from a variety of sources – e.g., customer feedback, collaboration with the foundries, and features found … Read More