As a preferred carrier to data or energy, photonics technology is becoming broad and diverse. In IC design, silicon-photonics technology has been the enabler of new capabilities and has revolutionized many applications as Moore’s-based scaling started to experience a slowdown. It acts as new on-chip inductor in HPC design … Read More
Cadence Summit Highlights Automotive Market Dynamics and System Enablement
Cadence held a well-attended Automotive Summit where Cadence presented an overview of their solution and system enablement along with industry experts and established or startup companies sharing their perspective and product features from autonomous driving, LiDAR, Radar, thermal imaging, sensor imaging, and AI.… Read More
Emulation from In Circuit to In Virtual
At a superficial level, emulation in the hardware design world is just a way to run a simulation faster. The design to be tested runs on the emulator, connected to whatever test mechanisms you desire, and the whole setup can run many orders of magnitude faster than it could if the design was running inside a software simulator. And … Read More
Why Did Ambiq Micro Select HiFi-5 DSP IP for Next Generation MCU?
Ambiq Micro has built a family of voice processing MCU dedicated to battery powered, energy sensitive systems, supporting mobile application like wearable. The company is facing two strong challenges: support computationally intensive processing (NN-based far field) and speech recognition algorithms, while offering … Read More
Solving and Simulating in the New Virtuoso RF Solution
Cadence has done a good job of keeping up with the needs of analog RF designs. Of course, the term RF used to be reserved for a thin slice of designs that were used specifically in RF applications. Now, it covers things like SerDes for networking chips that have to operate in the gigahertz range. Add that to the trend of combining RF and… Read More
IBIS-AMI Model Generation Simplified
The increasing demand for data communication throughput between system components has driven the requirement for faster SerDes IP data rates. The complexity of the transmit (Tx) and receive (Rx) signal conditioning functions has correspondingly evolved. As a result, the simulation methodology for SerDes electrical interface… Read More
Highly Modular, AI Specialized, DNA 100 IP Core Target IoT to ADAS
The Cadence Tensilica DNA100 DSP IP core is not a one-size-fits-all device. But it’s highly modular in order to support AI processing at the edge, delivering from 0.5 TMAC for on-device IoT up to 10s or 100 TMACs to support autonomous vehicle (ADAS). If you remember the first talks about IoT and Cloud, a couple of years ago, the IoT … Read More
Meeting Analog Reliability Challenges Across the Product Life Cycle
Create a panel discussion about analog IC design and reliability and my curiosity is instantly piqued, so I attended a luncheon discussion at #55DAC moderated by Steven Lewis of Cadence. The panelists were quite deep in their specialized fields:… Read More
A True Signoff for 7nm and Beyond
The Tale of Three Metrics
Meeting PPA (Performance, Power and Area) target is key to a successful design tapeout. These mainstream QoR (Quality of Results) metrics are rather empirical yet inter-correlated and have been expanded to be linked with other metrics such as yield, cost and reliability. While the recent CPU performance… Read More
Cadence Update on AMS Design and Verification at #55DAC
As a blogger in the EDA industry I get more invitations to meet with folks at DAC than I have time slots, so I have to be a bit selective in who I meet. When the folks at Cadence asked me to sit down and chat with Mladen Nizic I was intrigued because Mladen is so well-known in the AMS language area and he’s one of the authors of, The Mixed-Signal… Read More