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Cadence’s Strategic Leap: Acquiring Hexagon’s Design & Engineering Business

Cadence’s Strategic Leap: Acquiring Hexagon’s Design & Engineering Business
by Admin on 09-05-2025 at 8:00 am

Cadence Hexagon

In a bold move that underscores the accelerating convergence of electronic design automation (EDA) and mechanical engineering, Cadence Design Systems announced its agreement to acquire Hexagon AB’s Design & Engineering (D&E) business for approximately €2.7 billion, equivalent to about $3.16 billion. This… Read More


Cocotb for Verification. Innovation in Verification

Cocotb for Verification. Innovation in Verification
by Bernard Murphy on 08-27-2025 at 6:00 am

Innovation New

This time let’s see if we can stir up some lively debate. Cocotb isn’t new but it is an interesting alternative to mainstream testing methodologies. Paul Cunningham (GM, Verification at Cadence), Raúl Camposano (Silicon Catalyst, entrepreneur, former Synopsys CTO and lecturer at Stanford, EE292A) and I continue our series … Read More


A Big Step Forward to Limit AI Power Demand

A Big Step Forward to Limit AI Power Demand
by Bernard Murphy on 08-25-2025 at 6:00 am

Power estimation

By now everyone knows that AI has become the all-consuming driver in tech and that NVIDIA GPU-based platforms are the dominant enabler of this revolution. Datacenters worldwide are stuffed with such GPUs, serving AI workloads from automatically drafting emails and summarizing meetings to auto-creating software and controlling… Read More


Streamlining Functional Verification for Multi-Die and Chiplet Designs

Streamlining Functional Verification for Multi-Die and Chiplet Designs
by Daniel Nenni on 08-14-2025 at 6:00 am

Streamlining Functional Verification for Multi Die and Chiplet Designs

As multi-die and chiplet-based system designs become more prevalent in advanced electronics, much of the focus has been on physical design challenges. However, verification—particularly functional correctness and interoperability of inter-die connections—is just as critical. Interfaces such as UCIe or custom interconnects… Read More


Chiplets and Cadence at #62DAC

Chiplets and Cadence at #62DAC
by Daniel Payne on 08-12-2025 at 10:00 am

SoC Cockpit Concept min

Using chiplets is an emerging trend well-covered at #62DAC and they even had a dedicated Chiplet Pavilion, so I checked out the presentation from Dan Slocombe, Design Engineering Architect in the Compute Solutions Group at Cadence. In a short 20 minutes Dan managed to cover a lot of ground, so this blog will summarize the key  points.… Read More


Prompt Engineering for Security: Innovation in Verification

Prompt Engineering for Security: Innovation in Verification
by Bernard Murphy on 07-30-2025 at 6:00 am

Innovation New

We have a shortage of reference designs to test detection of security vulnerabilities. An LLM-based method demonstrates how to fix that problem with structured prompt engineering. Paul Cunningham (GM, Verification at Cadence), Raúl Camposano (Silicon Catalyst, entrepreneur, former Synopsys CTO and lecturer at Stanford,… Read More


New Cooling Strategies for Future Computing

New Cooling Strategies for Future Computing
by Daniel Payne on 07-17-2025 at 10:00 am

thermal panel dac min

Power densities on chips increased from 50-100 W/cm2 in 2010 to 200 W/cm2 in 2020, creating a significant challenge in removing and spreading heat to ensure reliable chip operation. The DAC 2025 panel discussion on new cooling strategies for future computing featured experts from NVIDIA Research, Cadence, ESL/EPFL, the University… Read More


Sophisticated soundscapes usher in cache-coherent multicore DSP

Sophisticated soundscapes usher in cache-coherent multicore DSP
by Don Dingee on 07-16-2025 at 10:00 am

A Tensilica 2 to 8 core SMP DSP adds cache-coherence for high-end audio processing and other applications

Digital audio processing is evolving into an art form, particularly in high-end applications such as automotive, cinema, and home theater. Innovation is moving beyond spatial audio technologies to concepts such as environmental correction and spatial confinement. These sophisticated soundscapes are driving a sudden increase… Read More


Reachability in Analog and AMS. Innovation in Verification

Reachability in Analog and AMS. Innovation in Verification
by Bernard Murphy on 06-26-2025 at 6:00 am

Innovation New

Can a combination of learning-based surrogate models plus reachability analysis provide first pass insight into extrema in circuit behavior more quickly than would be practical through Monte-Carlo analysis? Paul Cunningham (GM, Verification at Cadence), Raúl Camposano (Silicon Catalyst, entrepreneur, former Synopsys… Read More


A Novel Approach to Future Proofing AI Hardware

A Novel Approach to Future Proofing AI Hardware
by Bernard Murphy on 06-11-2025 at 6:00 am

Tensilica NeuroEdge min

There is a built-in challenge for edge AI intended for long time-in-service markets. Automotive applications are the obvious example, while aerospace and perhaps medical usage may impose similar demands. Support for the advanced AI methods we now expect – transformers, physical and agentic AI – is not feasible without dedicated… Read More