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Artificial Intelligence
A new look at fault localization and repair in debug using learning based on deep semantic features. Paul Cunningham (Senior VP/GM, Verification at Cadence), Raúl Camposano (Silicon Catalyst, entrepreneur, former Synopsys CTO and now Silvaco CTO) and I continue our series on research ideas. As always, feedback welcome.
I recently read a thought-provoking article in Quanta titled Chatbots Don’t Know What Stuff Isn’t. The point of the article is that while large language models (LLMs) such as GPT, Bard and their brethren are impressively capable, they stumble on negation. An example offered in the article suggests that while a prompt, “Is it true… Read More
AI-generated chip design is progressing at an incredible pace!
Earlier this week, I wrote about the Efabless AI Generated Open–Source Silicon Design Challenge. If you haven’t done so already, take a closer look at the challenge and see first-hand what this is all about. In talking to Mike Wishart and Mohamed Kassem, co-founders… Read More
I have observed before that the success of an AI engine at the edge rests heavily on the software interface to drive that technology. Networks trained in the cloud need considerable massaging to optimize for smaller and more specialized edge devices. Moreover, an AI task at the edge depends on a standalone pipeline demanding a mix… Read More
According to some AI dreamers, we’re almost there. We’ll no longer need hardware or software design experts—just someone to input basic requirements from which fully realized system technologies will drop out the other end. Expert opinions in the industry are enthusiastic but less hyperbolic. Bob O’Donnell, president, founder… Read More
As we all know design starts are the life blood of the semiconductor industry, both big and small. Enabling those design starts is what the semiconductor ecosystem is all about and Efabless has a very unique value proposition in this regard.
Efabless is a free cloud-based chip design platform, growing community of 9000+ chip designers,… Read More
It was refreshing to hear a talk focused on emerging stronger from the downturn when the news and media are focused on the gloom. At the recent Siemens EDA User2User conference, Joe Sawicki, executive vice president, IC, gave an uplifting keynote talk to the audience. He highlighted a secular growth trend happening in the semiconductor… Read More
Given popular fascination it seems impossible these days to talk about anything other than AI. At CadenceLIVE, it was refreshing to be reminded that the foundational methods on which designs of any type remain and will always be dominated in all aspects of engineering by deep, precise, and scalable math, physics, computer science… Read More
“Strategy” is a word sometimes used loosely to lend an aura of visionary thinking, but in this context, it has a very concrete meaning. Without a strategy, you may be stuck with decisions you made on a first-generation design when implementing follow-on designs. Or face major rework to correct for issues you hadn’t foreseen. Making… Read More
There were quite a few announcements at the TSMC Technical Symposium last week but the most important, in my opinion, were based on TSMC N3 tape-outs. Not only is N3 the leading 3nm process it is the only one in mass production which is why all of the top tier semiconductor companies are using it. TSMC N3 will be the most successful node… Read More
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Rapidus, IBM, and the Billion-Dollar Silicon Sovereignty Bet