Accellera Tackles Functional Safety, Mixed-Signal

I managed a few meetings at DVCon this year in spite of the Coronavirus problems. One of these was with Lu Dai Chairman of Accellera. I generally meet with Lu each year to get an update on where they are headed, and he had some interesting new topics to share.

Membership and headcount remain pretty stable. Any changes (at the associate level) are more in composition as some join for new areas, some drop out as their topic of interest wraps up.  Since DVCon is Accellera’s show, Lu walked me through conference status by region. DVCon US happened, but was noticeably cut back since both Cadence and Synopsys dropped out. DVCon China was cancelled (surprise, surprise) and we’ll have to wait to see what will happen to the DVCon Europe show (Oct 27-28). These are strange times.

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On a brighter note they have two new functional working groups, on functional safety and UVM AMS. Functional safety started as a proposed working group late last year and became a full working group in February. UVM AMS also moved pretty quickly from proposed working group to full working group. Lu said that the detail in the proposals and contribution from participants convinced them pretty quickly that both these topics were ready to be developed more fully.

Functional Safety
Functional safety work within Accellera is attracting a lot of support, sometimes from companies that haven’t been involved with Accellera before. Lu didn’t want to tell me who, but I did notice that Bosch is listed as an associate member. I’m told there are now 19 companies participating in the working group. I’m not surprised there is momentum behind standards here. ISO 26262 is famously good at defining what in general you must demonstrate, without getting into details of how you do that. Good for them but that leaves a lot of freedom, some of it unnecessary, in how builders comply. Adding more guidelines can only be a good thing.

Lu told me a big focus area is traceability of requirements between stages – architecture to implementation. He said he has personal experience of this need on one of his own projects. When they aim to certify functional safety, they’re asked to provide traceability. Right now they have no tool to automate that task, to trace between assets in the specs, their architecture, design and development flows.

Without automation and structure this is a lot of overhead and still comes down to trust. That’s OK when you’re dealing with someone you’ve worked with for many years, but not when you want to expand to new customers. Take testing as an example. You might start with a high-level spec in PDF. Then you write your test plan in a vendor tool flow, or maybe in Excel or some in-house format, then you implement the test plan, perhaps in Verilog. When you run the test, some of it runs in C on a processor for which you can’t get coverage, but you can get a logfile dump. Then you have to demonstrate fault coverage, say in an FMEDA. How do you convince your customer that their higher-level safety specs map down cleanly into what you have done? Even if you can, you’ve proven compliance for your tool flow but what happens if your customer wants to integrate components tested with other sets of tools? This is an area ripe for standardization and for automation.

UVM-AMS
On AMS, Lu told me he has an analog designer friend who expresses frustration that Accellera develops lots of “toys” for the digital folks but nothing for people like him. Apparently he’s not the only one concerned. According to Lu, pent-up demand culminated at DVCon Europe last year (there are a lot of analog designers in Europe). He said the analog voice is still a minority but it has become very consistent (and perhaps insistent).

Accellera held an open session in which some groups shared proposals and others expressed interest in participating in working groups. It became quite was pretty clear there were concrete things that could be done. One point they were all clear on is that the methodology they propose should be language-independent, working for both SystemC and SystemVerilog. The next milestone is a whitepaper, intended to be released in October, though the virus and travel constraints might have something to say about that date.

Lu also briefly mentioned progress on PSS 1.1, not enough for me to comment since I missed the tutorial unfortunately. Generally, I’m happy to see they are working on some important areas!

WEBINAR: Portable Stimulus: Moving UVM Verification Up To The Next Level

Also Read:

Functional Safety Comes to EDA and IP

Accellera IP Security Standard: A Start

Semiconductor IP Security Issues