Mixel Makes Major Move on MIPI D-PHY v2.5

The MIPI Alliance has been running hard since 2003 to stay on top of the changes in the mobile industry. MIPI now has 250 member companies and 12 active working groups, all focused on creating standards for connecting the building blocks in mobile systems. MIPI based interfaces are now used in cars, drones, IoT devices, and of course phones and tablets, among other things.

A lot has changed since 2003. Higher resolution cameras are common and increasing numbers of cameras are used in new systems. Frequently, leading-edge cars have 8 cameras and multiple displays. Also interface operating distance has increased. Often cameras and displays in cars are several meters away from application processors. Of course, power requirements are a constant factor for any mobile system.

The latest D-PHY v2.5 specification from MIPI was approved in October of 2019. It includes many new features that all address newer mobile system requirements. The Fast Bus Turnaround (BTA) feature lets systems use the same link for high speed data and also sending commands back in the reverse direction, reducing the number of wires needed.

Another important new feature is Alternate Low Power (ALP), which replaces the legacy Low Power signaling mode. It reduces power consumption on links up to 4 meters by lowering signaling voltage. The combination of BTA and ALP allows implementation of Unified Serial Link (USL) which is supported by MIPI CSI-2 v3.0, released in September of 2019. It offers an in-band control mechanism where there is no need for a separate set of wires and connections for a command line.

Mixel has just announced its D-PHY v2.5 IP with these new features and is backwards compatible with the earlier v2.1, v1.2 and v1.1 versions. It offers 1 clock lane and 4 data lanes. With these lanes running at 4.5 Gbps, the aggregate for the PHY is 18 Gbps. It can be configured as a MIPI Master or MIPI Slave, supporting CSI-2 and DSI/DSI-2 applications. Their D-PHY can switch during normal operation between high power and low power operation, and the bidirectional lanes can switch direction. These mode and direction changes can be performed without glitching or data loss.

Mixel takes the approach of offering the digital Control and Interface Logic (CIL) as a soft IP view in the form of RTL and STA constraints. The mixed signal portion is provided as hard IP that includes GDS, CDL, LEF and LIB. This unique approach of a combination of hard and soft IP promises to offer design flexibility and easier implementation.

The Mixel D-PHY v2.5 offering is impressive because the spec approval was just in October. Mixel has a good track record of proven silicon, with previous MIPI PHY IP delivered successfully on 9 different nodes at 8 different foundries.

MIPI based systems are increasingly important because of the diversity of their applications. Having standards for connecting mobile processors and their peripherals improves performance and reduces costs for suppliers and consumers. To learn more about the new Mixel D-PHY v2.5 IP offering I suggest looking at the announcement on their website.

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