The Latest in Parasitic Netlist Reduction and Visualization

The Latest in Parasitic Netlist Reduction and Visualization
by Tom Dillinger on 10-22-2018 at 12:00 pm

The user group events held by EDA companies offer a unique opportunity to hear from designers and CAD engineers who are actually using the EDA tools “in the trenches”. Some user presentations are pretty straightforward – e.g., providing a quality-of-results (QoR) design comparison when invoking a new tool feature added to a recent… Read More


Advanced Materials and New Architectures for AI Applications

Advanced Materials and New Architectures for AI Applications
by Tom Dillinger on 10-17-2018 at 7:00 am

Over the past 50 years in our industry, there have been three invariant principles:

  • Moore’s Law drives the pace of Si technology scaling
  • system memory utilizes MOS devices (for SRAM and DRAM)
  • computation relies upon the “von Neumann” architecture
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Neural Network Efficiency with Embedded FPGA’s

Neural Network Efficiency with Embedded FPGA’s
by Tom Dillinger on 09-21-2018 at 12:00 pm

The traditional metrics for evaluating IP are performance, power, and area, commonly abbreviated as PPA. Viewed independently, PPA measures can be difficult to assess. As an example, design constraints that are purely based on performance, without concern for the associated power dissipation and circuit area, are increasingly… Read More


Analytics and Visualization for Big Data Chip Analysis

Analytics and Visualization for Big Data Chip Analysis
by Tom Dillinger on 08-28-2018 at 12:00 pm

Designers require comprehensive logical, physical, and electrical models to interpret the results of full-chip power noise and electromigration analysis flows, and subsequently deduce the appropriate design updates to address any analysis issues. These models include: LEF, DEF, Liberty library models (including detailed… Read More


An update on the Design Productivity Gap

An update on the Design Productivity Gap
by Tom Dillinger on 08-03-2018 at 12:00 pm

Over a decade ago, a group of semiconductor industry experts published a landmark paper as part of the periodic updates to the International Technology Roadmap for Semiconductors, or ITRS for short (link). The ITRS identified a critical design productivity gap. The circuit capacity afforded by the Moore’s Law pace of technology… Read More


Accelerating the PCB Design-Analysis Optimization Loop

Accelerating the PCB Design-Analysis Optimization Loop
by Tom Dillinger on 08-01-2018 at 12:00 pm

With the increasing complexity and diversity of the mechanical constraints and electrical requirements in electronic product development, printed circuit board designers are faced with a number of difficult challenges:

  • generating accurate (S-parameter) simulation models for critical interface elements of the design
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1-on-1 with Anirudh Devgan, President, Cadence

1-on-1 with Anirudh Devgan, President, Cadence
by Tom Dillinger on 07-27-2018 at 12:00 pm

At the Design Automation Conference, no one is busier than an EDA company executive — conference panels, product launch briefings, customer meetings, and corporate dinners all place considerable demands on their time. I was fortunate enough to be able to meet with Anirudh Devgan, President of Cadence, at the recent DAC55 in San… Read More


Autonomous Driving and Functional Safety

Autonomous Driving and Functional Safety
by Tom Dillinger on 07-25-2018 at 12:00 pm

The timelines proposed by automobile manufacturers for enabling fully autonomous driving are extremely aggressive. At the recent DAC55 conference in San Francisco, I attended a panel discussion on Functional Safety issues for assisted and autonomous driving, sponsored by Mentor Graphics. I also had the opportunity to chat… Read More