Writing the unwritten rules with ALINT-PRO-CDC

Writing the unwritten rules with ALINT-PRO-CDC
by Don Dingee on 02-09-2015 at 11:30 am

EDA verification tools generally do a great job of analyzing the written rules in digital design. Clock domain crossings (CDCs) are more like those unwritten rules in baseball; whether or not you have a problem remains indefinite until later, when retaliation can come swiftly out of nowhere.

Rarely as overt or dramatic as a bench-clearing… Read More


Inside tips on Tanner L-Edit toolbox

Inside tips on Tanner L-Edit toolbox
by Don Dingee on 02-02-2015 at 7:00 am

Advanced skill in auto repair, carpentry, plumbing, and similar trades often correlates to one factor. Knowing what you want to do is one thing – having the proper tool is another, and can make the difference. Many a job has extended from minutes to hours over the lack of the right tool at the right moment. Experienced mechanics and… Read More


Xilinx ships the VU440 and its 4M logic cells

Xilinx ships the VU440 and its 4M logic cells
by Don Dingee on 01-27-2015 at 8:00 pm

Xilinx has delivered not only “the biggest FPGA on the planet”, but what it claims is currently the world’s largest integrated circuit: the Virtex UltraScale VU440, with 19 billion transistors fabbed in TSMC 20nm. The list of first customers to receive parts says a lot about the state of SoC design today, and the vital role FPGA-based… Read More


How Imagination tested the PowerVR Series6XT

How Imagination tested the PowerVR Series6XT
by Don Dingee on 01-23-2015 at 10:00 pm

We have been hearing for some time about the Synopsys HAPS-70 and how they have co-created the hardware and software architecture for FPGA-based prototyping with their customers. Now, we see details published by Synopsys on how they collaborated with Imagination on the design of the PowerVR Series6XT GPU.

The first thing to come… Read More


Aldec increasing the return on simulation

Aldec increasing the return on simulation
by Don Dingee on 01-19-2015 at 10:00 pm

Debate rages about which approach is better for SoC design: simulation, or emulation. Simulation proponents point to software saving the need for expensive hardware platforms. Emulation supporters stake their claims on accuracy and the incorporation of real-time I/O. A few years back, some creative types coined the term SEmulation,… Read More


Tracing methods to multicore gladness

Tracing methods to multicore gladness
by Don Dingee on 01-18-2015 at 9:00 am

Multiple processor cores are now a given in SoCs. Grabbing IP blocks and laying them in a multicore design may be the easy part. While verification is extremely important, it is only the start – obtaining real-world performance depends on the combination of multicore hardware and actual application software. What should engineers… Read More


Makers get access to Intel RealSense

Makers get access to Intel RealSense
by Don Dingee on 01-08-2015 at 11:00 pm

One of the great devices in maker lore is the Polaroid 6500 Series Sonar Ranging Module. It was originally part of the autofocus system for their SX-70 cameras circa 1978, long before through-the-lens optical autofocus sensors were perfected. Back then, people couldn’t focus. Dr. Land thought he was teaching people to compose… Read More


Lights, audio, and waiting for action from Qualcomm

Lights, audio, and waiting for action from Qualcomm
by Don Dingee on 01-06-2015 at 3:30 pm

The news Qualcomm has shipped over a billion Snapdragon chips in Android smartphones broke last September. After reiterating that and a sustained outlook for smartphones over the next five years, the Qualcomm CES 2015 presser seemed to leave most media outlets a bit disappointed. Naturally, that prompts us to ask what is going… Read More


SoCs should invest in a strong cache position

SoCs should invest in a strong cache position
by Don Dingee on 12-30-2014 at 4:00 pm

Like most technology firms, Apple has been home to many successes, and some spectacular defeats. One failure was Project Aquarius. At the dawn of the RISC era, before ARM architecture was “discovered” in Cupertino, engineers were hunkered over a Cray X-MP/48. The objective was to design Apple’s own quad core RISC processor to … Read More


Verilog-AMS connects T-SPICE and Riviera-PRO

Verilog-AMS connects T-SPICE and Riviera-PRO
by Don Dingee on 12-20-2014 at 7:00 am

With advances in available IP, mixed signal design has become much easier. Mixed signal verification on the other hand is becoming more complicated. More complexity means more simulation, and in the analog domain, SPICE-based techniques grinding away on transistor models take a lot of precious time. Event-driven methods like… Read More