Author: Daniel Payne

Posted on

Variation-Aware Design: A Hands-on Field Guide

Variation-Aware Design: A Hands-on Field Guide
by Daniel Payne on 12-01-2012 at 2:57 pm
Categories: EDA, Solido

IC designers using advanced nodes are acutely aware of how variation effects in the silicon itself are causing increased analysis and design efforts in order to yield chips at acceptable levels. Four authors from Solidoare so passionate about this topic that they combined their years of experience into a book that I had a chance… Read More

Posted on

ASIC Prototyping: Dini Group and Tektronix

ASIC Prototyping: Dini Group and Tektronix
by Daniel Payne on 11-25-2012 at 7:00 pm
Categories: EDA

Collaboration in EDA is nothing new, however you may not be aware of how the Dini Group and Tektronix have worked together on an FPGA prototyping platform to address issues like debugging with full visibility across an entire multi-FPGA design. At SemiWiki we’ve blogged a couple of times so far about the new debug approach… Read More

Posted on

Internet of Things, My Bluetooth Headset

Internet of Things, My Bluetooth Headset
by Daniel Payne on 11-20-2012 at 8:42 pm
Categories: IP

A catchy phrase used by bloggers and journalists these days is “Internet of Things“, or IoT if you prefer acronyms. All of this is made possible by EDA tools in the hands of SoC designers to create useful products like my Jawbone ICON bluetooth headset. Tonight I discovered that I could customize my bluetooth headset… Read More

Posted on

What I Learned About FPGA-based Prototyping

What I Learned About FPGA-based Prototyping
by Daniel Payne on 11-15-2012 at 8:10 pm
Categories: Aldec, EDA, FPGA

Today I attended an Aldec webinar about ASIC and SoC prototyping using the new HES-7 Board. This prototyping board is based on the latest Virtex-7 FPGA chips from Xilinx.

You can view the recorded webinar here, which takes about 30 minutes (should be available in a few days). I first blogged about the HES-7 two months ago, ASIC Prototyping… Read More

Posted on

Static Timing Analysis for Memory Characterization

Static Timing Analysis for Memory Characterization
by Daniel Payne on 11-11-2012 at 6:18 pm
Categories: EDA, Synopsys

Modern SoC (System On Chip) designs contain a larger number of RAM (Random Access Memory) instances, so how do you know what the speed, timing and power are for any instance? There are a couple of approaches:
[LIST=1]

  • Trust the IP supplier to give you models that use polynomial equations to curve-fit the performance numbers based
    • … Read More
    Posted on

    Chip On Wafer On Substrate (CoWoS)

    Chip On Wafer On Substrate (CoWoS)
    by Daniel Payne on 11-03-2012 at 5:19 pm
    Categories: EDA, Foundries, Siemens EDA, TSMC

    tsmc cowos test vehicle1

    Our EDA industry loves three letter acronyms so credit the same industry for creating a five letter acronym CoWoS. Two weeks ago TSMC announced tape-out of their first CoWoS test chip integrating with JEDEC Wide I/O mobile DRAM interface, making me interested enough to read more about it. At the recent TSMC Open Innovation Platform… Read More

    Posted on

    Electromigration (EM) with an Electrically-Aware IC Design Flow

    Electromigration (EM) with an Electrically-Aware IC Design Flow
    by Daniel Payne on 11-03-2012 at 4:05 pm
    Categories: Cadence, EDA

    fig2a

    Electromigration (EM) is a reliability concern for IC designers because a failure in the field could spell disaster as in lost human life or even bankruptcy for a consumer electronics company. In the old days of IC design we would follow a sequential and iterative design process of:… Read More

    Posted on

    Improving FPGA Prototype Debugging

    Improving FPGA Prototype Debugging
    by Daniel Payne on 10-30-2012 at 10:00 am
    Categories: EDA

    FPGA Prototyping is growing in popularity as a method to get an SoC design into hardware running at clock speeds up to 100MHz or so. One downside during traditional FPGA prototyping debug is the limited number of internal signals that you can observe while trying to chase down bugs in the hardware design in the presence of running … Read More

    Posted on

    An AMS Reference Flow for Power Management Designs

    An AMS Reference Flow for Power Management Designs
    by Daniel Payne on 10-26-2012 at 5:42 pm
    Categories: Cadence, EDA

    At DAC in June I visited and blogged about 30+ EDA and Semi IP companies, however I didn’t have time to watch the TowerJazz presentation in the Cadence Theater entitled: AMS Flow for Power Management Designs. Today I watched the 26 minute video and have summarized what I learned in this blog post.… Read More