Last year I was surprised at DAC by an un-heard of EDA company from China, ICScape. This year I followed up and spoke with Ravi Ravikumar about what’s new with ICScape in 2013.… Read More
EDA Tools from China at DAC
Author: Daniel Payne
Validating Hard IP & Std Cell Libraries at DAC
The building blocks for every SoC are standard cell libraries that are assembled, designed and verified together. But how do we really know if all the data formats used during design are correct and consistent? To answer that question I spoke with Johan Peetersof Fractal Technologiesat DAC.
Johan Peeters, Rene Donkers
… Read More
A 3D Field Solver for Parasitic Extraction Thermal ESD Analysis
The smaller the process node the more necessary it is that you extract accurate parasitics from interconnect and 3D structures in order to analyze timing, thermal effects and ESD compliance. Silicon Frontlinehas EDA tools in all three of these categories, so I met with Dermott Lynchat DAC to get an annual update.
Dermott Lynch,… Read More
An EDA update from Dassault Systemes at DAC
I first met Michael Munseyback at Viewlogic in the 1990’s, so was pleased to meet with him at DACand get an update on what Dassault Systemes has to offer the EDA world.
Michael Munsey, Dassault Systemes
SPICE update from ProPlus at DAC
With EDA tool development in San Jose, Beijing and China, ProPlusis probably best known for their device modeling software called BSIMProPlus. At DAC I met with Lianfeng Yang, Ph.D. the VP of Marketing to hear about what’s new.
Lianfeng Yeng, ProPlus
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Circuit Simulation update from Cadence at DAC
I’m keenly interested in SPICE circuit simulators, so at DACI met with John Piercefrom Cadence to get an update on what’s new this year.
John Pierce, Cadence
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Visual AMS Debug, an update at DAC
If you’re involved with AMS or transistor-level IC design then having visual tools will help you design and debug quicker. At DAC I met with Gerhard Angst, President and Founder of Concept Engineering to get an update.
Gerhard Angst (center), Concept Engineering… Read More
Full Visibility in ASIC Prototypes at DAC
ASIC prototyping from multiple vendors using FPGA boards was popular at DAC again this year in Austin, Texas. I stopped by the Tektronix booth for a few minutes to meet with Dave Orecchio to get an update.
Dave Orecchio (right), Tektronix… Read More
Fujitsu, Mediatek, Richtek and Synopsys om Custom IC Design
Synopsys has been acquiring EDA and IP companies at a fast clip over the past few years and it’s often made me wonder how they are going to craft a coherent tool flow for custom IC design. At DACthis year I learned that for schematic capture the winning tool is Custom Designer SE– a relatively new tool, while the IC layout… Read More
Static Low-Power Verification in Mixed-Signal SoC Designs
IC designer Shubhyant Chaturvediof AMD used EDA tools from Mentor Graphicsand Concept Engineeringto perform static, low-power verification of a mixed-signal SoC design with a combined CPU and GPU. Shubhyant presented a poster session at DAC two weeks ago in Austin, and I wanted to share it with my readers here at SemiWiki.… Read More
Intel Wildcat Lake: Right-Sizing Silicon Without Sinking Performance