With many design teams still searching for an effective means of identifying Charged Device Model (CDM) issues early in the design process, it comes as no surprise that events on this topic generate a lot of interest and are well attended. In July Magwel’s CEO Dr. Dundar Dumlugol had the honor of being invited by Professor Ming-Dou… Read More
Author: Daniel Nenni
WEBINAR: AI-Powered Automated Timing Arc Prediction for AMS IP’s
A directed approach to reduce Risk and improve Quality
Safety and reliability are critical for most applications of integrated circuits (ICs) today. Even more so when they serve markets like ADAS, autonomous driving, healthcare and aeronautics where they are paramount. Safety and reliability transcend all levels of an integrated… Read More
Automatic Documentation Generation for RTL Design and Verification
Ask any hardware or software engineer working on a product, and they will tell you that writing documentation is a pain. Customers have high expectations for user manuals and reference guides, usually requiring a team of technical writers to satisfy their requirements. In order to meet time-to-market deadlines, documentation… Read More
AI Chip Prototyping Plan
I recently had the opportunity to sit down with a chip designer for an AI start-up to talk about using FPGA prototyping as part of a complex silicon verification strategy. Like countless other chip designers for whom simulation alone simply does not provide sufficient verification coverage, this AI start-up also believed that… Read More
TSMC OIP Overview and Agenda!
The TSMC Symposium and OIP Ecosystem Fourm are the most coveted events of the year for the fabless semiconductor ecosystem, absolutely. In my 35 years of semiconductor experience never has there been a more exciting time in the ecosystem and that is clear by the overview and agenda for this year’s event. I hope to see you there:… Read More
Carnegie Robotics Case Study: RTLvisionPRO
RTLvisionPRO has proven to be an indispensable tool which has greatly improved the productivity and work-flow of our current task: understanding, verifying, and documenting the existing RTL IP library at our company. Consisting of about 500 Verilog and VHDL files, the library has been under development for several years and… Read More
WEBINAR: Lightspeed Data Sync – Design Workspace Problems Solved!
With every process node and every SOC design, engineering and IT teams are experiencing an unprecedented data explosion. User workspaces routinely exceed 10’s of GB and sometimes even 100’s of GB. Regression runs, characterization runs, design and debug of workspaces, building verification environments – all of these… Read More
WEBNAR: How ASIC/SoC Rapid Prototyping Solutions Can Help You!
If you are considering an FPGA prototype for an ASIC or SoC as part of your verification strategy, which more and more chip designers today are doing to enhance verification coverage of complex designs, please take advantage of this webinar replay:
How ASIC/SoC Prototyping Solutions Can Help You!
Or to get a quick quote from S2C … Read More
Low Power Design – Art vs. Science
I have heard many times before that low power and mixed-signal design is more Art than Science. I believe this is a misconception. Science is a field that builds upon previous experiences and discoveries. Art primarily seeks out creative differences, things we have not seen before that evoke emotion. The most successful designers… Read More
Webinar – Fabless: The Transformation of the Semiconductor Industry 2019 Update!
As more than 343 people (and counting) know, we will be releasing the 2019 updated PDF version of our first book “Fabless: The Transformation of the Semiconductor Industry” via handout at a live webinar. The response has been overwhelming and I want to personally thank you. The webinar will be a brief overview of the book with a question… Read More










The Name Changes but the Vision Remains the Same – ESD Alliance Through the Years