Extreme-ultraviolet lithography is essential for manufacturing advanced semiconductor devices, but its continued scaling presents a difficult materials problem. Photoresists must simultaneously provide high resolution, low exposure dose, limited line-edge or linewidth roughness, and extremely low defectivity. … Read More
Author: Admin
Reducing EUV Exposure Dose Through Underlayer Engineering
The Twelve-Month Rule Does Not Describe a New Fab
By Nikhil Shah
Capital spending is often treated as if it becomes semiconductor capacity about twelve months later. That can be a useful rule for equipment installed in an existing fab. It is a poor description of a new fab built from the ground up.
I tested the distinction using five advanced-node projects in the United States where… Read More
Latest Savage on Security Webinar Focuses on Gen-AI for Chip Design and Security
Key Takeaways from the webinar:
Multi-agent intelligent assistant systems of the future will be architected to automate and augment SoC design and security verification and redefining semiconductor innovation, reshaping design, verification and security for the next generation of trusted silicon.
The ESD Alliance is delighted… Read More
Boost Front-End SoC Design With Defacto’s AI-Powered Tool
Front-end SoC design has always been a balancing act between speed, accuracy, and the large amount of manual work required to get RTL, IPs, and collaterals to be aligned. In a recent webinar, Defacto CEO and founder Chouki Aktouf joined by product manager Valentin Boyer, walked through how the company is bringing AI directly into… Read More
How early symmetry validation eliminates costly late-stage respins
By Mauli Shah, Product Engineer, Siemens
Analog and mixed-signal design teams face a persistent challenge that directly impacts tape-out schedules and project predictability: symmetry violations discovered at signoff trigger expensive respins, delay schedules and create unpredictable iteration cycles. Despite symmetry… Read More
Rethinking Formal Verification in the AI Era
By Kanav Arora, ML Researcher at ChipAgents
Most hardware teams already understand why formal verification matters. It can expose corner cases that simulation may never reach and establish critical behaviors across the modeled state space.
The unresolved question is not whether formal works. It is why formal remains a specialist… Read More
How Fast Can a Performance Model Actually Be Built?
By Thang Tran, CEO of Simplex Micro and Umesh Sisodia, CEO of CircuitSutra
Performance models have a reputation problem. They’re often treated as a long-lead, high-effort undertaking — something a design team commits to early and then waits on for months before it’s useful. The development of SimplEx Micro’s… Read More
Enhancing Multi-Domain System Simulation with FMI Co-Simulation
As systems become increasingly complex across every field of science and engineering, the importance of computer simulation in design, analysis, and verification continues to increase over time. The traditional process in which a system is modeled and simulated in a single tool is called monolithic simulation. On the other… Read More
GPU-native mask rule checking eliminates the curvilinear mask rule check bottleneck
As semiconductor manufacturing pushes toward advanced nodes with tighter feature sizes, the optical proximity correction (OPC) workflow is adopting curvilinear masks to achieve the larger process windows that traditional Manhattan geometries cannot deliver.
Traditional Manhattan masks constrain shapes to vertical … Read More
John Barr: The EDA Veteran and Award-Winning Needham Funds Portfolio Manager
John Barr, Portfolio Manager of the top-ranked Needham Aggressive Growth Fund, has built a career with skills honed not just on Wall Street, but in the trenches of the early EDA industry.
Before becoming a respected sell-side analyst and later a buy-side portfolio manager, Barr spent 15 years in the EDA industry, working through… Read More









The $725 Million Chip Development: Why Execution Risk, Not IP Cost, Now Dictates Advanced-Node Survival