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Threads

Securing RISC-V Third-Party IP: Enabling Comprehensive CWE-Based Assurance Across the Design Supply Chainby Jagadish Nayak RISC-V adoption continues to accelerate…Read More

Apple’s iPhone 17 Series 5G mmWave Antenna Module Revealed to be Powered by Soitec FD-SOI SubstratesRecent independent teardown and technical analyses have confirmed…Read More

World First 8nm 128Mb Embedded STT MRAM for Automotive

Advancing Automotive Memory: Development of an 8nm 128Mb Embedded STT-MRAM with Sub-ppm Reliability IEDM 2025 Papers MRAM…Read More

AI Drives Strong Semiconductor Market in 2025-2026The global semiconductor market in 2025 was $792…Read More

How Customized Foundation IP Is Redefining Power Efficiency and Semiconductor ROIAs computing expands from data centers to edge…Read More

‹›

Podcast EP334: The Unique Benefits of LightSolver’s Laser Processing Unit Technology with Dr. Chene Tradonsky

Podcast EP334: The Unique Benefits of LightSolver’s Laser Processing Unit Technology with Dr. Chene Tradonsky
by Daniel Nenni on 03-06-2026 at 10:00 am
Categories: CEO Interviews

Daniel is joined by Dr. Chene Tradonsky, a physicist and the CTO and co-founder of LightSolver, where he leads the development of a proprietary physics-based computing system built on coupled laser dynamics to accelerate compute-heavy simulations and other computationally demanding workloads. Before moving into physics,… Read More

March 6, 2026March 6, 2026

Global 2nm Supply Crunch: TSMC Leads as Intel 18A, Samsung, and Rapidus Race to Compete

Global 2nm Supply Crunch: TSMC Leads as Intel 18A, Samsung, and Rapidus Race to Compete
by Daniel Nenni on 03-06-2026 at 6:00 am
Categories: Foundries, Intel Foundry, Samsung Foundry, TSMC

TSMC 2NM Intel 18A Samsung 2nm Rapidus 2nm

The semiconductor industry is in the midst of a structural supply challenge that’s tightly coupled to exploding demand for advanced chips, especially those used in AI, HPC, and next-generation mobile and consumer devices. At the center of this vortex is the 2nm class of manufacturing technology, representing one of the most … Read More

March 5, 2026March 3, 2026

Reducing Risk Early: Multi-Die Design Feasibility Exploration

Reducing Risk Early: Multi-Die Design Feasibility Exploration
by Kalar Rajendiran on 03-05-2026 at 10:00 am
Categories: 3D IC, Chiplet, EDA, Synopsys

The semiconductor industry is entering a new era in system design. As traditional monolithic scaling approaches its economic and physical limits, multi-die architectures are emerging as a primary pathway for delivering continued improvements in performance, power efficiency, and integration density. By distributing … Read More

March 5, 2026March 4, 2026

From Satellites to 5G: Ceva’s PentaG-NTN™ Lowers Barriers for Terminal Innovators

From Satellites to 5G: Ceva’s PentaG-NTN™ Lowers Barriers for Terminal Innovators
by Daniel Nenni on 03-05-2026 at 8:00 am
Categories: Ceva, IP

Ceva, Inc., a leading provider of silicon and software IP for the Smart Edge, has unveiled PentaG-NTN™, its groundbreaking 5G Advanced modem IP subsystem tailored for satellite user terminals in Low Earth Orbit (LEO) and Medium Earth Orbit (MEO) constellations. Announced at Mobile World Congress 2026 in Barcelona on March 3,… Read More

March 5, 2026February 26, 2026

Siemens Reveals Agentic Questa

Siemens Reveals Agentic Questa
by Bernard Murphy on 03-05-2026 at 6:00 am
Categories: AI, EDA, Siemens EDA

There’s no denying that verification now leads the field in agentic AI announcements, accelerating the trend around this significant contribution to design automation. Siemens have just announced their Questa One Agentic Toolkit, their response to this trend, building on the core Questa One platform. Questa One provides … Read More

March 4, 2026March 3, 2026

Functional Safety Analysis of Electronic Systems

Functional Safety Analysis of Electronic Systems
by Daniel Payne on 03-04-2026 at 10:00 am
Categories: EDA, Siemens EDA

Safety engineers, hardware designers and reliability specialists in safety-critical industries like automotive, aerospace, medical device and industrial automation use FMEDA (Failure Modes, Effects and Diagnostic Analysis). ISO 26262 compliance for ADAS, braking systems and ECUs require FMEDA in the automotive sector.… Read More

March 4, 2026March 3, 2026

RVA23 Ends Speculation’s Monopoly in RISC-V CPUs

RVA23 Ends Speculation’s Monopoly in RISC-V CPUs
by Jonah McLeod on 03-04-2026 at 8:00 am
Categories: IP, RISC-V

RVA23 marks a turning point in how mainstream CPUs are expected to scale performance. By making the RISC-V Vector Extension (RVV) mandatory, it elevates structured, explicit parallelism to the same architectural status as scalar execution. Vectors are no longer optional accelerators bolted onto speculation-heavy cores.… Read More

March 4, 2026March 3, 2026

Perforce and Siemens Collaborate on 3DIC Design at the Chiplet Summit

Perforce and Siemens Collaborate on 3DIC Design at the Chiplet Summit
by Mike Gianfagna on 03-04-2026 at 6:00 am
Categories: 3D IC, EDA, Events, Perforce, Siemens EDA
1 Comment

The recent Chiplet Summit at the Santa Clara Convention Center was buzzing with many enabling technologies for chiplet-based design. Collaboration was also on display during many parts of the show. A presentation in the Siemens booth was a perfect example of both of those trends. In the Siemens booth, Perforce presented an excellent… Read More

March 3, 2026March 3, 2026

Building the Interconnect Foundation: Bump and TSV Planning for Multi-Die Systems

Building the Interconnect Foundation: Bump and TSV Planning for Multi-Die Systems
by Kalar Rajendiran on 03-03-2026 at 10:00 am
Categories: 3D IC, Chiplet, EDA, Synopsys

UCIe bump planning in 3DIC Compiler Platform

The first article in this series examined how feasibility exploration (hyperlink to SemiWiki first article) enables architects to evaluate multi-die system configurations while minimizing early design risk. Once architectural decisions are validated, designers must translate conceptual connectivity requirements … Read More

March 3, 2026March 2, 2026

CHERI: Hardware-Enforced Capability Architecture for Systematic Memory Safety

CHERI: Hardware-Enforced Capability Architecture for Systematic Memory Safety
by Daniel Nenni on 03-03-2026 at 8:00 am
Categories: CHERI, Security

The rapid escalation of cyberattacks over the past two decades has exposed a fundamental weakness at the core of modern computing systems: the lack of memory safety. Industry data consistently shows that the majority of critical software vulnerabilities stem from memory corruption issues such as buffer overflows, use-after-free… Read More

An AI-Native Architecture That Eliminates GPU Inefficiencies
The statement that the branch behavior of GPGPU applications is incorrect. GPGPUs do not allow each thread to follow a…

— Todd B. on March 5, 2026
A Detailed History of Samsung Semiconductor
Awesome! Very well researched and explained. I learned a lot!

— runawaymo on March 4, 2026
Perforce and Siemens Collaborate on 3DIC Design at the Chiplet Summit
An example of PLM2PLM Interation liking Hub-The-Spoke

— yanfeng on March 4, 2026
Memory Matters: Signals from the 2025 NVM Survey
What about putting memory on a separate chiplet? Is that tied to increasing bit capacity?

— Fred Chen on March 3, 2026
Advancing Automotive Memory: Development of an 8nm 128Mb Embedded STT-MRAM with Sub-ppm Reliability
Gotta note the fine print: read failure is ppm-level, not sub-ppm. This is also pointed out in the paper and…

— Fred Chen on March 2, 2026
Advancing Automotive Memory: Development of an 8nm 128Mb Embedded STT-MRAM with Sub-ppm Reliability
The key question is whether changing your SoC or MCU design to 8nm to include 128 Mb (or larger) eMRAM…

— Fred Chen on March 1, 2026
The Name Changes but the Vision Remains the Same – ESD Alliance Through the Years
Thanks for the additional history Dave, much appreciated. You are correct about the broad charter of EDAC. I remember participating…

— Mike Gianfagna on February 28, 2026
The Name Changes but the Vision Remains the Same – ESD Alliance Through the Years
Nice article. A few updates for accuracy sake: The organization was founded by Rick Carlson and Dave Millman as IDAC,…

— davemillman on February 27, 2026

Semitracks Course: Semiconductor Reliability and Product Qualification

GOMACTech 2026

embedded world 2026

SNUG Silicon Valley

LID Silicon Valley 2026

Podcast EP334: The Unique Benefits of LightSolver’s Laser Processing Unit Technology with Dr. Chene Tradonsky

Global 2nm Supply Crunch: TSMC Leads as Intel 18A, Samsung, and Rapidus Race to Compete

Reducing Risk Early: Multi-Die Design Feasibility Exploration

From Satellites to 5G: Ceva’s PentaG-NTN™ Lowers Barriers for Terminal Innovators

Siemens Reveals Agentic Questa

Functional Safety Analysis of Electronic Systems

RVA23 Ends Speculation’s Monopoly in RISC-V CPUs

Perforce and Siemens Collaborate on 3DIC Design at the Chiplet Summit

Building the Interconnect Foundation: Bump and TSV Planning for Multi-Die Systems

CHERI: Hardware-Enforced Capability Architecture for Systematic Memory Safety

Recent Forum Threads

US Considers Requiring Permits for Nvidia, AMD Global AI Chip Sales

Intel CEO Tan reconsidering fate of chipmaker's new manufacturing tech, CFO says

Intel Foundry’s Advanced Packaging Innovations Lead the Industry in Scaling Past Reticle Limits

Build China’s ASML

Rapidus Corporation today announced that it has completed a funding round totaling $1.7 billion USD from the Japan government and private sector

Intel has manufacturing capacity issues. They may take years to fix.

OpenAI amends Pentagon deal as Sam Altman admits it looks ‘sloppy’

I'm having trouble understanding Broadcom's claimed AI revenue results and projections

How a Taiwanese VC Broke Into the Commercial Space Industry

US lawmakers raise concerns over Intel's testing of tools made by Chinese-linked firm

Recent Article Comments

An AI-Native Architecture That Eliminates GPU Inefficiencies

A Detailed History of Samsung Semiconductor

Perforce and Siemens Collaborate on 3DIC Design at the Chiplet Summit

Memory Matters: Signals from the 2025 NVM Survey

Advancing Automotive Memory: Development of an 8nm 128Mb Embedded STT-MRAM with Sub-ppm Reliability

Advancing Automotive Memory: Development of an 8nm 128Mb Embedded STT-MRAM with Sub-ppm Reliability

The Name Changes but the Vision Remains the Same – ESD Alliance Through the Years

The Name Changes but the Vision Remains the Same – ESD Alliance Through the Years