Performance Modeling Engineer

Arteris enables engineering and design teams at the world’s most transformative brands to connect and integrate today’s system-on-chips (SoCs) that fuel modern innovation.

If you’ve held a smartphone, driven an electronic car, or powered up a smart TV, you’ve come in contact with what we do at Arteris. Here, the future is quite literally in your hands—and when it isn’t, chances are it is flying overhead in a drone, a satellite, or in the cloud at a datacenter!

Do you want to contribute to the backbone of some of the world’s most popular SoCs?

As a Performance Modeling Engineer at Arteris, you will work with an expert team to design and deliver interconnect & memory hierarchy solutions for some of the world’s most sophisticated mobile, telecom, automotive, and consumer SoC products. You will model complex configurable designs and produce performance analyses that drive architectural decisions. You will provide customers with performance analysis and estimation solutions. You will go home at the end of the day amazed at all the places where your creations end up. You will have the opportunity to be part of a proven, successful startup, and to influence development environment, architecture, verification, and everything in-between – you will no longer be stuck in a silo or just a cog in the machine. Your co-workers will be an experienced team of industry experts that love what they do.

Required:

• You are the kind of person that brings your intelligence, motivation, and sense of humor to the office.
• 7+ years of experience in developing software performance models in one or more of the following: CPUs, GPUs, networking on chip, or equivalent.
• 7+ experience in driving architecture and microarchitecture improvements using performance model analyses.
• 7+ years’ experience in SystemC, C++, and/or TLM2.0.
• Strong problem solving, debugging, and brainstorming skills.

Desired:

• Familiarity with ARM processors and on-chip interfaces such as OCP & AXI.
• Strong knowledge of cache coherency protocols.
• Experience with code generators to create configurable hardware descriptions.
• Experience with scripting languages such as TCL/Perl/Python etc.

Estimated Salary Compensation:

• $150,000 to $195,000 annually

About Arteris:

Arteris is a leading provider of system IP for the acceleration of system-on-chip (SoC) development across today’s electronic systems. Arteris network-on-chip (NoC) interconnect IP and SoC integration automation technology enable higher product performance with lower power consumption and faster time to market, delivering better SoC economics so its customers can focus on dreaming up what comes next.

With over 250 employees with headquarters in Silicon Valley and offices around the globe, we are a catalyst for SoC innovation so companies ranging from startups to the biggest technology market leaders can effectively create new products with proven connectivity flexibility and ease.  Learn more at arteris.com.