A couple of misconceptions about FD-SOI

We have extensively discussed in Semiwiki about FD-SOI technology, explaining the main advantages (Faster, Cooler, Simpler), sometimes leading to very deep technical discussions, thanks to Semiwiki readers and their posts. I have recently found an article “Samsung & ST Team Up on 28nm FD-SOI”. This article includes many quotes from so-called “analysts” or experts, that I will share and comment with you in a minute. Why taking the time to do so? Because some of these quotes are just simply wrong!

First Quote (in theory)
Also part of the enticement to designers wanting to dive into FD-SOI is that staying with 28nm mode means, in theory, no new non-recurring engineering costs. In other words, the 28nm masked set transfers to the 28nm FD-SOI and no $50-million-plus redesign needs to happen as you would see with a jump to new process node.

If you read and trust this assertion, you may jump to one of the ASIC supplier, ST or Samsung, supporting FD-SOI technology, bring your existing SoC mask set in 28nm bulk and be quite frustrated. At first, the design rules may not be compatible at all: FD-SOI is derived from 28nm HKMG gate-first process, when most of the 28nm bulk ASIC technologies are based on gate last (TSMC for example). Even if the existing design targets 28nm HKMG gate-first process, a new layout would be required to be adapted to some FD-SOI specificities like wells configuration and polarization. Porting an existing design from 28nm Bulk to FD-SOI with no layout modification is not realistic, furthermore it would be a mistake! If you want to take full benefit of the various FD-SOI advantages, you certainly don’t want to miss the capability of using the Forward Body Bias (FBB) effect. With no layout modification, you could not implement the polarization scheme and not benefit from FBB.

Just take a look at the above table. Applying FBB allow reducing maximum power consumption (dynamic + leakage), up to 31% for the same technology node (14FD-SOI) and slow conditions… and up to more than twice power consumption for the device in 28HPM with ASV. This power consumption reduction is almost magic, but it is unrealistic to think you can blind port a bulk design to FD-SOI, you will need a new mask set.

The latest point about porting an existing design: ASIC supplier like ST has automated the porting, creating scripts which translate schematics and automatically modify layouts. Thus the automated migration path allows porting an existing IP in ½ (half) to 1/3 (one third) of the time it would have required to port the IP in a new technology. Finally, the design must be tuned-up in order to have correct electrical behavior.

To summarize: for an existing design on bulk, if you want to benefit from the better power consumption (or better performance) linked to Forward Body Bias capability on FD-SOI, you will have to modify the existing layout, thus create a new mask set. The porting can be automated and the result must be tuned-up to have correct electrical behavior.

Second quote (you don’t get the strength)
Kevin Krewell of Tirias Research told EE Times. “FD-SOI offers power benefits but you don’t get the strength.” He explained that the process does work well for wearables where the idle power is most important. FD-SOI gives just enough performance to handle a wearable’s work and small display but it reduces the power to extend the battery life (…)

I love the second quote: it’s a mix of true fact (FD-SOI offers power benefits) and completely wrong interpretation (FD-SOI gives just enough performance to handle a wearable’s work and small display) of this fact. We have written a blog to address such interpretation, If you think that FD-SOI is for low performance only, but it could be wise to address this point again. At first, we have mentioned in Semiwiki some ASIC designed on 28nm FD-SOI targeting performance hungry networking application and you can check in this recent blog for the mention of ST design-win of a communication infrastructure ASIC in 14nm FD-SOI… not really a wearable device!

Yes, you can get the strength with FD-SOI technology. Moreover, you can compensate the slow process corners and avoid doing binning (binning from Wikipedia: “by reducing the clock frequency or disabling non-critical parts that are defective, the parts can be sold at a lower price, fulfilling the needs of lower-end market segments”), improving the SoC profitability. Eliminating “Slow” process corner device is possible, but extremely costly as a chip maker pays for the complete wafer. Using adaptive supply voltage (ASV) is a way to keep high performance at the same level for any chips, even coming from a slow process corner. Using forward body bias (FBB) can be a way to reduce the SoC power consumption, or to increase performance, at your choice.

In fact, using FD-SOI technology to design for wearable devices, or for smartphone is certainly a good option, thanks to the performance efficiency offered by the technology. But that doesn’t mean that an ASIC built in FD-SOI technology “don’t get the strength” and is limited to low power/low performance system. Speaking about an existing ASIC in bulk technology, you will benefit from FD-SOI advantages without doing a full redesign, by doing a simple porting. The effort is comparable to this done in the past to shrink a SoC, requiring a new mask set, like for a shrink…This effort will be largely paid by the power AND performances benefits given by FBB, unique to FD-SOI.

The quoted article can be found here

From Eric Esteve from IPNEST