Is That PDK Safe to Use Yet?

In our semiconductor ecosystem we have foundries on one side supplying all of that amazing silicon technology, and IC designers on the other side that take their system ideas then go implement them in a SoC using a specific foundry. The required interface between foundry and chip designers has been the Process Design Kit (PDK), a collection of files that define how the silicon should work:

• SPICE models for transistor behavior
• Layout Parasitic Extraction (LPE) decks that define the physical interconnect in terms of resistors, capacitors and inductor
• Design Rule Checks (DRC) that define how the physical IC layout should be done in order to yield properly
• Layout Versus Schematic (LVS) decks that specify how transistor-level netlists should compare between layout and logical

Getting the PDK files right is really important because with small process nodes we have Layout Dependent Effects (LDE), for example the Vt of one transistor depends on how close it is physically placed next to another transistor or even a contact. Same issue with the mobility of a transistor, it depends on physical placement. Parasitic values can now dominate the speed of a transistor, so knowing how to extract them properly impacts the accuracy of timing analysis tools..

We all know that software is mostly written by hand, so that means that bugs can creep into the tool by accident. Well, the PDK is just a bunch of files that can be manually or automatically generated, and yes, these files may be off a bit, so what to do? If you’re an automation company you would come up with a way to create a QA tool for PDK creators and PDK users. This is exactly what the engineers at Platform DA have come up with, a QA toolset for the foundries that create the PDKs and for the circuit designers that use PDKs. They call their tool PQLab, and I just learned more about it.

Related blog – Are your Transistor Models Good Enough?

A chip designer has certain questions about the PDK:

• What just changed when going from PDK v.1 to v.2?
• How does a PDK change impact my IC project?
• Which foundry should I use for my next IC design?
• Is there a way to benchmark different PDKs of two different design flows quickly?
• How does LDE, statistical variation and parasitics impact my design?

At the foundry the PDK engineering team has their own set of questions:

• Are all of my PCell combinations DRC clean?
• Will all of my PCell combinations be LVS clean?
• Can I compare the pre-layout versus post-layout circuit simulation results for typical cells?
• What just changed when going from PDK v.1 to v.2?

The approach used by PQLab is to help answer these questions through a set of QA features designed just for PDKs:

Starting with the DRC and LVS side of QA first, the idea is to automatically and randomly place cells from the Pcell library next to each other and then run a popular DRC/LVS tool like Calibre from Mentor Graphics to check that all combinations are actually clean and without any errors:

If DRC or LVS errors are found with certain cell combinations, then the foundry goes back and fixes those cell layouts and re-runs QA to ensure that each error has been fixed.

For the simulation QA there are three major tasks:

• Correlate SPICE models pre-layout versus post-layout
• Compare the device simulation specs like Vth, Idsat, etc. at pre-layout and post-layout conditions across a range of circuits
• Compare any differences between design flows with popular circuit simulators (HSPICE, Spectre) and extraction-based netlists from extractors (StarRC from Synopsys, Quantas QRC from Cadence, Calibre XRC from Mentor)

The third and final area of QA checking with the PQLab tool is PDK comparisons, where there are five criteria:

• PDK file comparison
• PCell property comparison
• CDF comparison
• PCell default layout and original position
• Simulation results comparison

Summary
PDK files continue to be the way that foundries and designers interface, so we need to be sure that all of the PDK files are consistent and correct. The PQLab tool from Platform DA provides the needed automation for PDK developers to ensure that they have the highest quality before releasing. IC designers can now quickly determine if a particular foundry PDK is going to provide them the performance and power requirements being sought and know what has changed between versions of a PDK. The QA process for a PDK doesn’t have to take weeks using semi-automated methods, now with some automation it can take only hours to complete. Foundries are using the PQLab tool to save time and produce PDK files that are solid.

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