MIPS 64 bit CPU Architecture

Imagination Technologies has just launched the 5[SUP]th[/SUP] generation of MIPS CPU core, the 64-bits Warrior, or I6400 family, offering a total compatibility with the 32-bit previous architecture. MIPS Warrior I-class processor cores offers 64-bit processing in applications including embedded, mobile, digital consumer, advanced communications, networking and storage. I6400 is designed to be an extremely flexible, low-power 64-bit processor architecture capable of scaling across a wide range of applications, from microcontrollers to 64-bit servers. This 64-bit architecture provides hardware virtualization in all cores, hardware multi-threading, multi-domain security and multicore/multi-cluster support.

If we take a look inside the I6400 family of cores, customers will benefit from:

• Highly efficient, scalable 64-bit performance:The I6400 will enable customers to set new price/performance points across markets. The I6400 can be implemented across a very wide range of performance, power and area operating points allowing reaching high frequencies in aggressive implementations. Design architect may implement multi cores and multi clusters configurations, including a mix of heterogeneous multi cluster, highly appreciable in mobile systems.
• Hardware multi-threading:The I6400 features hardware multi-threading technology that supports up to four hardware threads per core.

Hardware multi-threading leads to higher utilization and CPU efficiency. Moreover the simultaneous multi-threading (SMT) technology in the I6400 enables execution of multiple instructions from multiple threads every clock cycle. Preliminary benchmarking shows that adding a second thread leads to performance increases of 40-50% with less than a 10% cluster area increase.

• Hardware virtualization:To provide increase security and reliability and enable a unified security and virtualization strategy throughout the system, the I6400 joins the entire range of MIPS Warrior cores in incorporating hardware virtualization technology (this includes support for up to 15 secure/non-secure guests).

• Unified security strategy:The I6400 core is designed to address the privacy and security needs of evolving and emerging connected applications. The core is optimized to support multiple independent security contexts and multiple independent execution domains. The solution scales to support secure content delivery, secure payments, identity protection and more across multiple applications and content sources.
• Advanced power management:PowerGearing™ offer the ability to provide a dedicated clock and voltage level to each core in a heterogeneous cluster, while maintaining coherency across CPUs so that sleeping cores only need to wake when needed.
• Efficient FPU: The proven hardware Floating Point Unit (FPU) in the I6400 supports both single and double precision capabilities relevant to general computing as well as improved control systems processing.
• 128-bit SIMD:The I6400 features 128-bit SIMD support, delivering high performance and high throughput for a wide range of tasks that can exploit the efficiencies of SIMD execution in data-parallel applications. It is built on the MIPS SIMD architecture with instructions defined to be easily supported within high-level languages such as C or OpenCL for fast and simple development of new code, or to leverage of existing code.

Nothing is better than a picture (see above) and some numbers to illustrate the I6400 Power/Performance/Area (PPA) optimization. Targeting TSMC 28 HPM technology, the base core configuration, including 32 KB Instruction, 32 KB Data for the level 1 cache, two threads/core, SIMD/FPU and H/W virtualization with 15 guests, occupy one mm2 and deliver 5.6 CoreMark/Mhz or 3.0 DMIPS/Mhz. This performance level assuming worst case conditions (Vnom -10% and SS corner Silicon), nevertheless, higher frequencies can be achievable with more aggressive implementation techniques. The cluster configuration in this example is a quad core with 128 virtualized global interrupts and 1 MB of level 2 cache, for an estimated area of 7 mm2.

The successful semiconductor device will have to exhibit low power consumption while offering high performance, not only for mobile application but also in enterprise or consumer systems. Power efficiency (or performance in DMIPS or CoreMark per Watt) is the keyword. Advanced power management, or PowerGearing for MIPS I6400, is based on the following techniques:

• Fine grained, block level, and core level clock gating
• For each core (in multi-core cluster):

  • Sleep mode
  • Dynamic Voltage and Frequency Scaling (DFVS)
  • Can be implemented at different performance/power optimization point
• Directory-based coherency architecture optimized for low power

  • Sleeping cores only wake when needed for coherency

Imagination expects the industry to move for architecture neutrality, thus the CPU choice should be based on technical superiority. The I6400 features set addresses wide range of next generation applications, allowing customers to optimize their resource investment when targeting various applications.
Imagination is already engaged with multiple lead I6400 licensing partners, with general availability scheduled for December 2014. Contact info@imgtec.com for more information.

From Eric Esteve from IPNEST

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