It is free after you pay for it and there is a one-time annual fee: The Case for FD-SOI

In one of Portlandia’s TV program sketches, there is a funny interchange between a carrier salesperson and Fred Armisen (of SNL fame) who was trying to buy a phone. One chuckle line was a statement by the seller that the phone was free after paying for it and that there was a one-time annual fee. With this anecdote as a mental backdrop, the question for making the case for a new technology is: Is there a free gain? How much effort is really needed? The technology topic here is FD-SOI. This SOI exposé attempts to highlight the merits of FD-SOI (fully depleted Silicon-On-Insulator, and/or UTB-SOI, defined further below) which is now being looked as a viable technology offering since bulk CMOS is showing limits with technology node scaling. SOI technology is certainly not new in terms of having attractive leakage characteristics when compared to bulk C-MOS. The SOI consortium has announced a joint collaboration by ARM, Global Foundries, IBM, STMicroelectronics, Soitec, CEA- Leti to promote the FD-SOI technology and its value in mobile communication applications. The benefits are stated to be that Power/Performance metrics are excellent specially at lower voltages, simpler manufacturing and lower leakage.

Joël Hartmann (Corp VP or front-end manufacturing and process R&D at STMicroelectronics) made a compelling case for FD-SOI at the latest GSA Silicon Summit in April and he highlighted that this technology is a main contender now that the bulk C-MOS is reaching its feature size limits (beyond 20nm that is) where short channel effects make bulk unworkable. ST is counting on FD-SOI at least for its 28nm and 20nm road map and will have products this year using 28nm FD-SOI. The industry’s alternative choice for advanced nodes is FinFET and was discussed earlier by Paul McLellan. Beyond bulk, fully depleted devices will be needed for improved electrostatic control. FD-SOI can be further turbo-charged by adding ultra thin box back body bias (UTB-SOI) with added performance specially at lower voltages. In the same event, Dr Chenming Hu succinctly outlined the main differences between FinFET and UTB-SOI in that for FinFET the body thickness has to be less than the gate length Lg with larger Ion current and foundry investments, whereas the UTB-SOI requires thickness less than 1/3 the gate length, with a good back-bias option and SOI supplier investments. The arguments in favor of FD-SOI as stated by STMicroelectronics are:

[*=1]the use of the same Back-end process,
[*=1]only 20% of FD-Specific Front end process needs new development,
[*=1]wafer costs (process and substrate) are similar,
[*=1]10% better lead-time is achievable,
[*=1]no added Capex are needed since the same equipment is used,
[*=1]the process is portable through shrink and scalable to 14nm.

In the future FinFETs can also be built on top of SOI. The STMicro charts below illustrate how much power and performance can be gained using the UTB-SOI technology. At 1.0V 28nm FD-SOI with back bias can achieve a 94% performance boost over 28LP and at 0.6V a remarkable 730% improvement can be seen. More impressively at low Vdd the energy efficiency in (DMIPS/mW) literally goes through the roof as evidenced in the upward tilt of the top left curve. These are compelling numbers that merit notice and explain the road map direction of STMicroelectronics.

It does thus appear, in an interesting way that performance and energy efficiency gains can be free after developments paid for them and that there is a one-time development fee that needs to stay annual to keep the bits pumping in the ever shrinking geometries. Now you also know that I will stretch words to fit my anecdote in the hope that you realize I am just word playing here to get you to read, to be informed and freely entertained.

References:
GSA Silicon Summit April 26, 2012 Mountain View, CA (The source for most of the graphics and data)
SOI technology for the GHz era – by G. G. Shahidi
Evaluation of a fully-depleted SOI for next generation Mobile Chips – by Horacio Mendez Executive Director, SOI Industry Consortium