WP_Term Object
(
    [term_id] => 98
    [name] => Andes Technology
    [slug] => andes-technology
    [term_group] => 0
    [term_taxonomy_id] => 98
    [taxonomy] => category
    [description] => 
    [parent] => 14433
    [count] => 12
    [filter] => raw
    [cat_ID] => 98
    [category_count] => 12
    [category_description] => 
    [cat_name] => Andes Technology
    [category_nicename] => andes-technology
    [category_parent] => 14433
    [is_post] => 1
)

32-bit MCUs Way to Go for IoT

32-bit MCUs Way to Go for IoT
by Majeed Ahmad on 02-18-2015 at 7:00 am

Cost, power and performance, and security are the fundamental ingredients of chip development for the Internet of Things (IoT) market and that 32-bit microcontrollers are a way forward to meet these basic requirements. That was the crux of the message from the webinar held by Andes Technology Corp. on February 10, 2015.

You can see the full webinar HERE.

“The 8-bit MCU standard is limited by peripherals and instruction set and it doesn’t offer the cost advantage in the IoT environment,” said Emerson Hsiao, Senior VP of Sales & FAE at Andes. “Moreover, memory interface in 8-bit MCUs lead to bottlenecks for both power and performance, so they don’t make sense for IoT devices.” He added that peripherals in Andes’ 32-bit processor cores operate at different power modes, and thus they optimize power consumption.

Hsiao said that the IoT market is constantly evolving and there are significant changes in the IoT landscape every year. So IoT chips should not only offer lower power and higher performance but they should also be future proof in terms of technology upgrades. Hsiao quoted touch-panel controllers as an example where 8-bit MCUs sufficed for the first-generation touchscreens. However, for second- and third-generation touch-panel controllers, more demanding gesture applications for smartphones and wearable devices necessitate more powerful 32-bit MCU cores.


Andes’ ultra-low-power processor core solutions

Hsiao also presented smart meters as a case study where a chip costs US$2-3 and features MCU, communication port, and sensor interface as primary components. So rather than saving a few cents in chip development with 8051, more advanced power-saving techniques offered by 32-bit MCU cores could lead to a lot more energy conservation in the end. Hsiao mentioned that there are 300 million smart meters only in China. That just shows the scale of energy conservation that power-efficient chips could bring to smart meter operation at large.

For security, Hsiao again used the smart meter case study and explained how a secure MCU system can carry out embedded code protection within end-user device. He said that smart meter devices are mostly vulnerable at the memory and JTAG levels, and showed how Andes cores could allow access to JTAG debug interface and ILM to secure embedded software and program data.

CPU and Memory Bottlenecks

For IoT and connected wearables, Hsiao emphasized the small gate count for saving die area and high performance with execution efficiency for designers needing an upgrade path from 8-bit cores that have been widely used in embedded applications during the past two decades. However, if there was a prominent theme in this webinar, it was how power is driving requirements for applications such as IoT, connected wearables and other flash-memory based requirements. And the fact that Andes’ low power solutions impact beyond the processor cores.

Hsiao said that Andes’ 32-bit MCU cores offer greater energy efficiency through power-saving modes that outnumber competitor solutions. “Andes employs PowerBrake technique that results in flash acceleration, which in turn, reduces power consumption and improves performance.” The PowerBrake technology is based on the variation in frequency scaling at 16 levels and has met industry benchmarks for both Coremark and DMIPS, he added.

The PowerBrake technology helps minimize the idle power through creating different power modes for the CPU. The creation of power profiles for different connect stages helps to optimize the power interface to CPU and thus lowers power consumption and improves performance horsepower.

Another power efficiency technology that Hsiao mentioned during the webinar was FlashFetch, which minimizes access to NOR flash memory and thus lowers power and enhances memory interface speed. FlashFetch memory acceleration technique records repeated code sequence in a structure called TinyCache for later fast accesses.


FlashFetch eases memory interface bottlenecks

TinyCache is different from traditional caches in a sense that it takes power consumption into account. It improves program execution efficiency by providing zero wait-cycle for instruction accesses, and at the same time, it helps in cutting the total power consumption of CPU and flash memory. So, while the power consumption contributed by the CPU slightly increases due to the additional logic for the TinyCache, the power use coming from flash memory is greatly reduced due to less number of accesses.

Moreover, if required, FlashFetch can allow instruction accesses to read ahead, thus speeding up the execution of sequential code. This feature supports 64-bit and 128-bit fetch widths of flash memory. Hsiao acknowledged that prefetch buffer helps in enhancing performance, but it also brings in redundant instructions that lead to increased power consumption.

Image Credit: Andes Technology Corp.

Majeed Ahmad is author of books Smartphone: Mobile Revolution at the Crossroads of Communications, Computing and Consumer Electronicsand The Next Web of 50 Billion Devices: Mobile Internet’s Past, Present and Future.