WP_Term Object
    [term_id] => 98
    [name] => Andes Technology
    [slug] => andes-technology
    [term_group] => 0
    [term_taxonomy_id] => 98
    [taxonomy] => category
    [description] => 
    [parent] => 14433
    [count] => 12
    [filter] => raw
    [cat_ID] => 98
    [category_count] => 12
    [category_description] => 
    [cat_name] => Andes Technology
    [category_nicename] => andes-technology
    [category_parent] => 14433

Webinar: How IoT Designs Driven by Cost Power Security

Webinar: How IoT Designs Driven by Cost Power Security
by admin on 02-08-2015 at 8:30 pm

 SoCs being developed for the fast growth Internet-of-Things market will sell for and operate on a small fraction of the power of mobile devices’ chips. More importantly, IoT SoCs will be far more vulnerable to hacker attacks than the much better protected chips in portable devices. As a result, designers developing SoCs targeting IoT applications face a set of challenges that require computing capability unique to this class of devices: (1) extensive power management functionality, (2) sensor data and network protocol stack processing, (3) detecting and thwarting security attacks, (4) and enabling all these functions in a silicon footprint no larger than an 8-bit alternative.

Andes Technology Corporation will host a webinar on Tuesday, February 10, 2015 at 10:00 AM Pacific Time, that will detail how IoT designs are driven by cost, power, and security. One IoT device example that will be described, the smart meter, serves to illustrate the importance of these design considerations. It contains an analog interface from a sensor providing voltage, current, and temperature readings. A microcontroller in the design performs the compute functions for the design. In addition, there is a communications port, power-line communications, Zigbee, or some form of RF interface. For program and debug the design typically comes with an interface to external PC.

The 8-bit processors first used in IoT applications have a simple CPU architecture and instruction set, developed in the early 1970s, suited to control applications 30 to 40 years ago. With the rise of the smart phone, the computing requirements changed dramatically and demanded a 32-bit architecture, that were designed in the late 1980s, able to run on rechargeable batteries. Both these processors are being applied to the new Internet-of-Things devices now coming on the market, but neither provides the adequate computing architecture and instruction set required by this next generation of products.

The 32-bit embedded processor of which there are a number of alternatives provides the compute power, but suffer the problem of being designed for applications that were the major market drivers of their day: the PC, set-top box, and the mobile phone, tablet, and variety of consumer devices—cameras, audio recorders, and so on. The functionality in these 32-bit processors has yet to deliver a hit end-IoT product, comparable to the smart phone. For example, activity trackers and smart watches fall short on power and end user capability.

What the Internet-of-Things requires is a 32-bit processor with an architecture that serves the demand for high performance, while providing the power savings needed to last long periods between recharge or to run on harvested power. This webinar presents one such 32-bit embedded processor system. Designed in 2005 from the ground up, the Andes Technology N8 MCU plus AE210 peripherals will be used to illustrate how new architectural features can achieve both performance and power savings in a gate count comparable to an 8-bit CPU. Two features that will be described to drive home the point are frequency scaling and flash acceleration, neither supported directly on existing 32-bit embedded CPUs.

To provide the demand for enhanced security, the presentation will also describe hardware functionality built into the new 32-bit architecture: data and address scrambling and differential power analysis protection. The first provides protection from hacks that target the interface between CPU and memory. The second protects from hacking the program by observing the power use signature of the CPU.

Please join the webinar on Tuesday, February 10, 2015 10:00 AM – 11:00 AM PST. To register, click here.

By Emerson Hsiao, Senior VP, Sales and Technical Service, North America Operations

Share this post via:


There are no comments yet.

You must register or log in to view/post comments.