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Migrating to Andes from 8051

Migrating to Andes from 8051
by Paul McLellan on 02-11-2014 at 5:21 pm

 The 8051 microcontroller has been around for years…decades in fact. It was originally developed in 1980 by Intel. Back then it required 12 clock cycles per instruction but modern cores use just one. While it is still widely used, mostly as an IP core for SoCs, it is running out of steam despite running over 50 times faster than Intel’s original core. The trend is for microprocessors to deliver more work per second, which can be done by doing more work per instruction or increasing the clock rate. The overall trend is certainly towards 32 bit.


One thing driving this trend is the move towards connectivity, the Internet of Everything (IoE) or the Internet of Things (IoT) depending on your choice of buzzword. A microcontroller like the 8051 doesn’t have enough compute power to run a full stack for internet access, WiFi access or cellular access and its memory interface both slows things down and consumes unnecessary power, and its address space is too small for the amount of memory these types of activities require.


Another power hog is security, and any embedded device with connectivity in the IoT world cannot ignore this since it is or will be subject to attacks. Keeping hackers at bay is a basic feature for any attached device.


The Andes family of microproessors spans a wide range from the N705 with a two-stage pipeline running at 240MHz, up to the N13 with a 13 stage pipeline running at over a GHz.

One unique features is FlashFetch. This adds two additional memories, one caches instruction prefetches from flash memory to keep the processor running at full speed and speeds up non-loop code accesses. The other is a tiny cache of 128B that speeds up loop accesses. Any loops smaller than 128B will run out of cache entirely, and lots of loops are like that in encryption algorithms, video encode/decode, just copying stuff around memory and so on. The result is performance/power ratio for all the processors is better than equivalent products from other processor vendors.


Of course there is a full development environment, AndesSight, development boards and a portfolio of associated IP to go along with the processor core itself, both silicon IP blocks and software stacks.

New products such as IoTs require more performance AND less power to provide wireless connectivity, touch interfaces, power management, etc.

  • An optimized MCU-memory interface is a key way to increase performance while reducing power consumption
  • Andes unique FlashFetch addresses the issue by reducing the number of accesses to Flash memory
  • Andes external prefetch buffer accelerates CPU performance
  • Securing your embedded SW code is imperative
  • A complete MCU design ecosystem improves your productivity


More articles by Paul McLellan…