BannerforSemiWiki 800x100 (2)
Semiconductor Expert Forum

Posted on

U2U Mentor Users’ Group

U2U Mentor Users’ Group
by Paul McLellan on 04-04-2012 at 10:58 am
Categories: EDA, Siemens EDA

Mentor’s U2U user group meeting in Santa Clara is next week on April 12th at the Santa Clara Marriott. For those of you on the east coast the Waltham U2U is on May 16th, and for Europeans the Munich U2U will be on October 25th. Registration is open for both Santa Clara and Waltham, and there is a call for papers for Munich.

The day starts with Wally Rhines keynote at 9am. I think Wally must have an entire organization doing nothing but produce keynotes since he does a lot, and each one is completely different. They tend to be full of interesting data and so, as a geek, I enjoy them immensely. There is no published title yet but I’ll be there anyway.

That is followed by a second keynote from Sameer Halpete, VP of VLSI Engineering, NVIDIA: Superphones to Supercomputers: The Quest for a Trillion Transistor SOC.

After lunch there is a panel session on 3D-IC, clearly one of the hot topics at the moment. We can go out (double patterning, EUV, e-beam) or up (2.5D, 3D) and probably both. On the panel are:

  • Don Kurelich of Mentor (moderator)
  • Paul D. Franzon of North Carolina State University
  • Ruebin Fuentes of Amkor Technology
  • Riko Radojcici of Qualcomm
  • Matthew Hogan of Mentor

From the keynotes until lunch and for the rest of the afternoon after the 3D panel there are 6 parallel tracks:

  • Custom IC/AMS
  • PCB flow
  • Place and route
  • Silicon test and yield analysis
  • Functional verification
  • Calibre

The day wraps up with a closing reception and if you fill in your feedback card you can win an iPad (one of the new ones).

Registration is free. The registration page is here. Lunch is provided.

Posted on

How Co-design of MEMS-IC Saves Time

How Co-design of MEMS-IC Saves Time
by Daniel Payne on 04-04-2012 at 10:18 am
Categories: EDA, Tanner EDA

I learned about MEMS layout automation at a webinar in December and plan to attend another webinar next week on April 10thwhere two companies have created a MEMS-IC co-design flow, Tanner EDA and SoftMEMS. The big challenge is to ensure that the MEMS and electronic parts of a new design will simulate correctly before committing to production by using co-design techniques. Just doing verification of MEMS separate from verification of the IC will not guarantee that the combined MEMS-IC will function, so you have to use co-design. By simulating the complex interaction between MEMS-IC you can verify correct operation, that’s why co-design saves time by getting the system correct the first time instead of multiple iterations.

Co-Design Tool Flow
Basic MEMS layout is done with the L-Edit tool from Tanner EDA, then SoftMEMS has added extensions to L-Edit for MEMS-specific layout tasks. Here’s what the overall co-design tool flow looks like:

This co-design flow has the crucial analysis steps to validate that both MEMS and IC are simulating correctly prior to production.


Layout Editing in MEMS Pro

Webinar Objectives
· Creation of 3D models of devices from Tanner EDA’s L-Edit layout for virtual prototyping
· Creation of MEMS-specific layouts using SoftMEMS extensions to L-Edit
· Links to 3D FEM/BEM simulators – such as ANSYS, COMSOL, Oefelie
· Simulation of MEMS/electronics using T-Spice with SPICE, Verilog-A and C-code
· Modeling of packaging effects on MEMS sensors
· MEMS-specific design rule checking

Tanner EDA
In the co-design flow the tools from Tanner EDA are: W-Edit, S-Edit, T-Spice, LVS, L-Edit, DRC.

SoftMEMS
Dr. Mary Ann Maher founded SoftMEMS in 2004 however before that she worked at Tanner EDA where the MEMS Pro tools where developed in 1997. Her company headquarters are in Los Gatos, CA and they have goups in both Grenoble, France and Cairo, Egypt. This France/Egypt connection reminded me of how Mentor Graphics acquired Anacad in Grenoble which also has a group in Egypt.

Webinar Details

This webinar is free however you do have to signup for it. Attend on Tuesday, April 10th at 8:30AM Pacific (11:30AM Eastern). If the webinar on MEMS-IC co-design looks like an interesting approach for your projects then you can consider evaluating the Tanner EDA tools at no cost.

Posted on

Jasper Asian Seminars

Jasper Asian Seminars
by Paul McLellan on 04-04-2012 at 1:38 am
Categories: EDA

Jasper has three seminars coming up in May in Hsinchu (Taiwan), Beijing and Shanghai. These are full-day seminars on how to solve critical verification challenges using state-of-the-art formal technology. Breakfast and lunch will be served.

This full-day tutorial will be given by technical experts for verification experts and will cover, among other things:

  • Formal verification of RTL blocks
  • Debug and design exploration
  • Post-silicon debug and root cause analysis
  • Verification of ARM-protocol based SoCs (AXI, AMBA, AHB, ACE)
  • Verification of SoCs with complex memory sub-systems (DDRxx)
  • Verification of designs including power-management structures
  • SoC and IP connectivity
  • Control status registers
  • Closure and coverage
  • Clock domain crossing
  • X-propagation


May 15 Hsinchu Taiwan
Sheraton Hotel
No. 265, Dong Sec. 1,
Guangming 6th Rd
Zhubei City 302
To register for this seminar contact Kay Lan at phone: 866-3-5739968 x21 email kay@kaviaztech.com


May 17 Beijing, China
Park Plaza Hotel
No. 25, Zhichun Road
Haidian District
Beijing
To register for this seminar contact 8610.8280-0729 ext. 8001 email bingfeng@ops-eda.com

May 18 Shanghai, China
Parkyard Hotel
No. 699, Bibo Road
Zhangjiang District
Shanghai
To register for this seminar contact 8610.8280-0729 ext. 8001 email bingfeng@ops-eda.com

Details of the seminars in Chinese are here.

Posted on

ARM big.LITTLE Virtual Platforms

ARM big.LITTLE Virtual Platforms
by Paul McLellan on 04-03-2012 at 7:11 pm
Categories: Arm, IP, Synopsys

You have probably heard something about ARM’s big.LITTLE architecture. This links a Cortex-A15 multi-core CPU with a Cortex-A7 CPU. The A15 is a high-performance processor and the A7 is a very low power processor. The basic idea is that when high-performance is required (playing a graphical video game on your smartphone, for example) then the A15 is brought into play and when high-performance isn’t needed (during a phone-call, for example) then the A7 is used. This gives the best of both worlds, a processor with high peak performance and very low average power.

It is worth noting that since the processor is often only a small part of the system, that running slowly, and thus keeping the whole system powered up for longer, is not always optimal. In some systems it is better to “race-to-halt” and run as fast as possible and then power-down the whole system until the next burst of activity.

Whether a task runs on A15 or A7 is not under control of the task, but instead it is handled dynamically by “task migration software” running underneath the operating system in a virtualization layer. So there is application software running on top of an operating system like Android running on top of a hypervisor, running on top of a multicore chip with two different performance levels. For the first time, application software at the top of the stack can have a major potential impact on power consumption (aka battery life).

The obvious answer to how to write software for any complex hardware is to use a virtual platform. The problem, as always, is availability of models. Synopsys have released a Virtualizer Development Kit (VDK) for this platform, incorporating high-speed models of the Cortex CPUs along with models of popular peripherals such as keyboard, touchscreen and ethernet. In fact they have created sort of starter kits which are virtual versions of ARM reference boards (which are not yet available in any case).

These virtual platform models are integrated with all the popular multi-core debuggers (don’t try and persuade a software engineer she can’t have the debugger she is used to) and additional instrumentation so that you can see what software is running on which core. Different systems might want different policies on this, from a high-performance system that primarily runs on A15 (big) and really only runs on A7 (little) when it is pretty much idle, to a system that runs mainly on A7 and only switches reluctantly to A15 when the A7 seems to be out of juice.

In multicore environments, virtual platforms offer some major advantages over hardware reference boards: they are deterministic and the whole system can be frozen. With multicore hardware, there is no guarantee that a bug will re-occur if the program is re-run. And if one core hits a breakpoint there is a delay before other cores can halt (“limited skid breakpoints”). With a virtual platform, rerunning the software with the same inputs will produce the same outputs, and reproduce the same bugs. And if you hit a breakpoint then all cores can be stopped to allow an in depth examination of the innards of what is going on.

The platform also allows a coarse level of power analysis, looking at the different power levels for each device depending on its state (so an LCD screen might be bright, dim or off).

Posted on

Conquering the Big Data Challenges

Conquering the Big Data Challenges
by Beth Martin on 04-02-2012 at 4:38 pm
Categories: EDA, Siemens EDA

Extrapolating the trends from last 20 years to the next ten suggests that we will be implementing a trillion transistors or more by 2020. At 20nm, with the chip sizes touching billions of transistors, the age old problem of how to implement a design in the most efficient manner remains unanswered.

Continue reading “Conquering the Big Data Challenges”

Posted on

DAC 2012 Technical Program Highlights

DAC 2012 Technical Program Highlights
by Daniel Nenni on 04-01-2012 at 11:00 pm
Categories: EDA, Events

The technical program for DAC 2012 has an exceptional quality of technical papers, panels, special sessions, WACI (Wild and Crazy Ideas), WIP (Work In Progress), full day tutorials and user-track. The program is tailored for researchers and developers focused on electronic design automation (EDA) and embedded systems and software, along with design engineers, and management. It highlights the advancements and emerging trends in the design of electronic circuits and systems.

The core of the technical program consists of 163 peer-reviewed papers with 35% of the content on ESS and 65% on EDA. Papers were selected from 742 submissions, the highest number of submissions to the conference in the past 5 years, and increase of 7% from 2011. Organized in the 35 technical paper sessions, these papers cover a broad set of topics ranging from system-level design, low power, physical design and manufacturing, embedded systems and software, logic and high level synthesis, simulation, verification, test and emerging technologies. Popular submission themes were:

[LIST=1]

  • Power analysis and low power
  • Physical Design and Design for Manufacturability
  • Architectures and Memory Design for Embedded Systems
  • ESS Design Methodologies
  • Emerging Technologies

    The submissions reflect that DAC has become the central conference to showcase tools and methodologies for traditional EDA design, Embedded Systems, and for Emerging Technologies.

    The technical program committee’s excitement about the technical content is reflected in the session titles, “Yin and Yang of Memories: the power-performance trade-off”, “Routing Rules!”, “Yielding in an Uncertain World”, “Why Model? Because reality is complicated enough!”, “Staying cool: modeling thermal effects in 3D and multi-core”, “Top Picks of Run-Time Power Management Techniques”, “SOS: Specification, Optimization and Synthesis in System-Level Design”, and “Design Automation for Things Wet, Small and Spooky”.

    SPECIAL SESSIONS:
    10 special sessions will deal with a wide variety of themes from physical design to embedded software, including progress in design closure, power at different levels of abstraction, heterogeneous platforms, probabilistic embedded computing, self-aware and Adaptive Technologies and neuromorphic computing.

    This year special sessions will also focus on how EDA can be applied to non classical EDA applications and problems such as the electronic counterfeit, wireless sensor networks design, medical devices designs.

    USER TRACK: (sponsored by Apache Design, an ANSYS subsidiary)
    The User Track highlights contributions by users of EDA and Embedded Systems tools and flows, targeting designers and practitioners: design tool users, hardware or software designers, application engineers, consultants, and flow or methodology developers.
    We have some exciting changes for the User Track this year. The Tuesday and Wednesday sessions will take place adjacent to the exhibit floor. In addition, one of the DAC keynotes is dedicated to the User Track this year. We have invited the project managers of two industry-leading chips to discuss their designs and associated design challenges. Both managers will bring some senior members of their staff for an interactive panel-Q/A session to be held the same day as their keynote.

    This year, we received 142 submissions, with authors from 90 institutions! The reviewing committee consisted of 35 industry experts representing user communities at 24 different companies. The User Track program includes the keynote, 8 paper sessions, 2 poster sessions, and the design panel session. The topics span embedded software to lithography and highlight challenges, solutions and methodologies covering verification, timing analysis, ASIC and FPGA design flows, IP block integration, test and debug.

    PANELS:
    For DAC 2012, a pervasive theme that panels address is: Have we reached a tipping point for a variety of technologies? High-level synthesis, system models, 3D chips, FPGA expansion, parallel EDA, and the cloud are technologies that have been discussed and researched for some time now; this year we separate the reality from the anticipation. Many DAC 2012 panels discuss whether each of these technologies is about to tip, taking off to become mainstream and thereby changing the face of the EDA industry. In addition, other panels address vexing issues like the impact of reliability, low-power design and automation, and the role of software versus hardware

    TUTORIALS:
    As in the past, the goal of the DAC tutorials is to provide practical, useable, and up-to-date knowledge that attendees can immediately apply in their jobs or studies. This year’s program includes six tutorials on timely subjects, including three system level topics – virtual platforms, system level power modeling, and high level synthesis; and three design topics – addressing 20nm design challenges, implications of 3DIC and Wide I/O on Design, and Analog / Mixed signal at advance process nodes.

    EXHIBIT FLOOR
    With over 200 exhibitors, including 21 first time exhibitors, this year’s exhibit floor offers exciting technologies and vendors to DAC attendees. New this year is the ARM Connected Community Pavilion, where attendees can visit ARM technology based demos from ARM partners. The exhibits are open Monday, Tuesday and Wednesday with the User Track presentations on Tuesday and Wednesday.

    EMBEDDED SYSTEMS & SOFTWARE (ESS) Executive Day 2012 (Wednesday, June 6)
    The ESS Executive Day is a day-long track of sessions dedicated to bringing industry stakeholders together in one room to shed light on where system design is headed. The day is comprised of presentations from leading industry executives representing the embedded development ecosystem. IC design engineers, embedded systems designers, embedded software and hardware IP providers, IP integrators, FPGA designers, investors, foundry reps, and the media will be on hand in this new forum to hear from market leaders and to network with each other.

    Presenters will focus on optimization of embedded and application-domain specific operating systems, system architecture for future embedded products, application-specific architectures based on embedded processors and technical/business decision making by program developers. They will cover the state-of-the-art solutions for embedded software and systems and complex chips. Such solutions often require tight collaboration between diverse players in this ecosystem. Moving to new levels of complexity can significantly affect the choices of suppliers. The new ESS Executive Day provides a unique opportunity to foster discussions that address all aspects of the embedded development ecosystem

    Management Day 2012 (Tuesday, June 5)
    The rubber meets the road at the intersection of low power Systems-on-Chip design and the adoption of emerging technologies. Management Day at the 49[SUP]th[/SUP] Design Automation Conference (DAC) provides engineering and business managers with essential information to make the right decisions at the intersection of business and technology.

    “Optimizing for volume production, low power, and shrinking sizes necessitates accurate trade-off analysis to drive technical/business decision-making,” said Yervant Zorian, 49[SUP]th[/SUP] DAC Vice Chair and Management Day Coordinator. “Moving to new semiconductor technology nodes such as 20nm can significantly affect the choices of suppliers. The Management Day sessions were designed to create lively dialog and to provide decision criteria to guide managers towards optimum choices from a pool of alternative options for flows, methodologies and suppliers.”

    Management Day at DAC 2012 will feature presentations by managers from independent device manufacturers (IDMs), fab-light ASIC providers, foundries, and fabless companies. Senior managers of today’s most complex nanometer SoCs will discuss the latest emerging solutions, along with their economic impact. A third panel session will involve the audience in an open brainstorming discussion and will complement the presentation sessions.

    • Posted on

    Intel will NOT build ARM chips!

    Intel will NOT build ARM chips!
    by Daniel Nenni on 04-01-2012 at 6:00 pm
    Categories: Arm, Foundries, Intel Foundry, IP

    As I mentioned in my previous blog “NVIDIA Claims TSMC 20nm will not Scale?” Jen-Hsun Huang is a very entertaining guy. I always listen to the NVIDIA conference calls because you never know what he will say next. Clearly he is a smart guy so you have to ask yourself why all the rhetoric?

    In the Forbes article NVIDIA: Intel should let us build chips in its factories, Jen-Hsun suggests that there would be “no shame”for Intel to be a foundry for all the mobile (ARM based) companies. Intel Atom is the only chance at breaking the ARM monopoly so the Intel response was obvious:

    “We have a small nascent foundry business, but our focus with our SOCs (systems on a chip) is really on Intel based platforms,” said Intel spokesman Jon Carvill. “Our process technology is a huge advantage going forward in 2012 and 2013, so our focus at this time is on building Intel products, not on building products for our competitors.”

    I know Jon Carvill, he comes from 5+ years at ATI/AMD and 2+ years at GLOBALFOUNDRIES, and I can assure you his actual response was probably much more entertaining, especially if he was drinking coffee at the time he heard this nonsense. But know this, Jon knows the GPU and Foundry business so take his words seriously, it’s not going to happen.

    Intel is not like Samsung, where they can whore foundry capacity to customers like Apple in order to make up margins on other products such as memory and screens. Intel foundry services are laser focused in support of their core microprocessor products, Atom SoCs, Xeon, etc… Intel’s first foundry customers are small FPGA companies for a reason, FPGAs are an important part of the advanced process ramping cycle.

    Moving forward Intel will no longer consider AMD as a competitor, if they ever really did. ARM is the enemy and the number one Intel competitive weapon is advanced process technology which they absolutely will not share with ARM or ARM based designs. As I mentioned in my forum post Top 10 Reasons Intel will NOT Succeed as a Foundry!, Intel signing an ARM manufacturing license agreement is as likely as me winning the Mega Millions Lottery (I did not buy a ticket).

    Remember three years ago when GLOBALFOUNDRIES launched, Jen-Hsun made a bunch of provocative public comments about potentially moving foundry business over to GF:
    “Global Foundries is a leading silicon foundry with advanced and outstanding processing technology,” Huang said. “We’re seriously evaluating and discussing about the possibilities of working with them.”     Source: The Inquirer (http://s.tt/155oc)

    Only to recant:
    “Globalfoundries is an AMD fab, right? Globalfoundries is AMD’s fab. Our strategy is TSMC,” said Jen-Hsun Huang, chief exec of Nvidia, in an interview with Cnet News web-site.

    This was done purely to rattle the cages of TSMC as he was never serious about making a switch. I see these comments very much in the same lens. Whenever he’s pissed off at TSMC over capacity, pricing, yield curve, allocation…whatever… he uses PR as a means of venting. I personally think this is the wrong approach and is anti collaborative but it does make for an interesting blogosphere. I would bet that Jen-Hsun’s ego is responsible for more blog advertising views than any other CEO in the semiconductor ecosystem!

    Posted on

    IC Layout Design at Qualcomm

    IC Layout Design at Qualcomm
    by Daniel Payne on 03-31-2012 at 6:54 pm
    Categories: Cliosoft, Dassault Systemes, EDA

    I first met Betty Pokerwinski of Qualcomm at LinkedIn in the group called IC Layout Designers. I post frequently on LinkedIn and a blog article on an EDA tool called Visual Design Diff from ClioSoft created quite a discussion, enough so that I contacted Betty to learn more about her IC layout group at Qualcomm.

    Questions and Answers

    Q: How long have you been at Qualcomm?
    A: Since 2003

    Q: What types of chips does your group work on?
    A: MSMs, CSM, APQ, are 90% of the work we contribute to.

    Q: What are the end markets for your chips (cellphones, tablets, etc.)?
    A: Mostly Cellphones but there are other products in our future.

    Q: How many chips a year are you responsible for?
    A: We are not responsible for the ‘chip’ level work. We provide the internal IPs of the chips listed above as noted in LinkedIn.

    Q: What is the complexity of the chips in transistor count?
    A: They are SOCs and quite complex.

    Q: What does your IC design flow look like?
    A: Mainly IP and of course includes DRC, LVS, Softcheck, LEF and sometimes DEF generations. Cadence tools for IC layout.

    Q: What part does data management play in your IC design flow?
    A: A very large part. Ever project is managed by Synchronicity DM.

    Q: Which ClioSoft tools are you using?
    A: VDD only.

    Q: How does the VDD tool help your project?
    A: This tool is quite remarkable and it is not exclusive to ClioSoft Design Management Software. It can run as a stand-alone tool. We are using Cadence with DesignSync to manage data and it works perfectly fine. The software also gives you an opportunity to save the results as a text file which could be saved as one of the design’s views. It’s great for historical data on the design. The tool can also be used for diffing layout views and we are now looking at using it for possibilities in diffing abstracts (as a quick means of checking for possilble LEF changes).

    Q: What other uses do you have for VDD?
    A: Example if the design engineer added a device or two and changed a port name or added a new port, these new changes would highlight in green and layout will see exacly what changed from previous version without question. If something was removed it would be highlighted in red in the old location.
    The VDD tool can also be used on layout views. One would have to decide if that would be worth the time depending on number of changes. It is great if one did a small eco and wants to verify that’s all that changed but I’d not use it for a final sign-off without going through much scrutization first. I do think it could have value though on LEF flows. We have a lot of tools in-house for LEF integreity but for the quick sanity check the VDD tool might have value here. Quickly do check on Abstract both current and previous and see where a change might have occurred. Because it is visually shown in red / green colors one can see if a shift occurred and can easily remedy it. Just a thought though I find most of the value on the schematic diff use. By the way, the VDD can also show these changes in a text file and I had thought that could be useful for saving as a view for historical data of a design.

    Q: For layout how do you check LEF versus GDSII? Are you using some XOR process?
    A: XOR process of GDSII is time consuming. LEFs are generated from abstracts which are of course generated from layout but what could be done is DIFF two abstracts to do a sanity check that pins have not move (or if moved was to expectations). One could do a diff of lef files too but many times when you discover that there are differences the text file doesn’t give you a quick picture on what changed. One then has to do further work such as GDS compares to see what movements happened. VDD tool can run diff on layouts or anything made of layers in moments. IT puts these changes in 2 colors so you can see old vs new instantaneously. For me it’s just faster and provides the layout designer the information they need to fix or confirm.

    Q: Is your group growing?
    A: It grew dramatically over past year from approx. 23 to 38.

    Summary
    Qualcomm uses IC tools from multiple vendors and integrates them into a cohesive EDA tool flow to create complex IP blocks used mostly in cell phones. Transistor-level IC design and layout is alive and well for the high-volume markets that Qualcomm serves.

    Also Read

    More Growth in EDA

    What Changed On My Transistor-Level Schematic?

    Manage Your Cadence Virtuoso Libraries, PDKs & Design IPs (Webinar)