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The Auto Industry Speaks @ Renesas DevCon

The Auto Industry Speaks @ Renesas DevCon
by Holly Stump on 10-23-2012 at 9:00 pm
Categories: Automotive, EDA, Events


This year’s Renesas DevCon in Orange County, CA kicked off yesterday with an impressive lineup of speakers, record attendance, and an increased focus on automotive.
“TheAuto Industry Speaks,” an Expert Panel organized by Martin Bakerof Renesas, featured:

  • Yoichi Yano, RenesasExecutive VP and Member of the Board, who early in his career designed the original 850 MCU, the world’s most popular automotive controller
  • Michael Grimes, Technical Fellow, Semi, MCU & Controller Architecture at General Motors
  • Ian Wright, CEO at Wrightspeed, former cofounder Tessla Motors
  • Bob Adams, Hardware Team Leader, Interior, Body and Security, at Continental
  • Mike Bourton, Founder of Grid2Home


Insights? Sustainable mobilityclearly emerged as one of the big challenges, requiring both technical solutions and government/infrastructure/other aspects. Ian commented: Burning oil is a problem; some vehicles burn natural gas; we focus on electric cars, but the problem is still energy! Michael Grimes: It’s the same as always, we need to be more efficient, but we’ve picked all the low hanging fruit, so it becomes more expensive to improve efficiency. Now, MPUs for state-dependent behavior (based on altitude, warm or cold engine, etc.) may help reduce energy consumption. Yano-san: Automotive MPUs used to consume a lot of power, now they consume less; this allows tens of MPUs per car. Bob: Electric vehicles are even more sensitive to electronics power (range problem). New opportunities in controller design to lower power consumption. Ian responded: But, electric cars consume lots of amps, the MPU power is negligible. Bob: We need infrastructure for charging vehicles, complex issues.

Money, money, money:spirited discussion of why $40K for an electrical vehicle (EV) comparable to a $20K auto! In defense: expensive batteries, motors, extra electronics, low tire rolling resistance, etc. Lots of redundancy: electric storage and fuel storage, more cooling systems, engines for electric and fuel. The bad news: “The MPUs cost nothing compared to other components. so Moores Law will not help us….nor will volume. We may get to fewer, larger chips per car, take some silicon costs out, but this is a small part.”

Panelists also discussed the types of vehicles that represent the biggest growth for electric or hybrid propulsion. Ian stated, yes, look for vehicles that use a LOT of fuel, such as heavy duty trucks; especially those with a lot of stop/start action like garbage trucks (3 year payback for them vs passenger cars, which today require 7 yrs or government subsidy for ROI.) Range anxiety is a huge problem for electrical cars. Big batteries increase weight and cost, as well as time to ROI so range-extended EVs are important, because they can use existing infrastructure (gas). Michael G: Range anxiety is very real; why Chevy Volt is successful. Mike B: Other technologies like solar, wind, must be stored, so battery technologies must evolve for many applications.

AUTOSAR:effective in addressing industry challenges? Mike G: Autosar is to automotive software as Windows is to pc software…..(laughter.) The general consensus was that Autosar does not achieve all goals, but achieves many of them: not perfect; definitely committee-developed; and its layered OS can represent significant overhead when in real time and need fast response. But, it’s the predominant architecture, helps manage complexity (100M lines of code per car typical), and is a good first step to unify the industry which is key. Note: many Tier 1 companies say they have taken Autosar and customized it.

Autonomous vehicleswere recently touted, will this be a revolutionary or evolutionary change? 2 years or 10? In fact, depending on how we define autonomous, many capabilities already available in the helped or aided category, like cruise control and backup visibility/ monitoring. Ian said, his cars have driver assistance like slip control and they could go further, but don’t; must use driver control as gospel to avoid liability, especially in the US. Panelists felt the time will come; safety must be considered; needs lots of computing power, but we have this technology. Opportunities: Lots more electronics!!! Much more throughput would need to be added. Wireless and infrastructure. Sensing as well as compute power. Power and heat management for added electronics. Yano-san commented that active safety and autonomous cars are definite roadmap drivers; constant balance needed re: capability and power consumption of chips (sensors and processors.) A very exciting area. Emerging opportunity for vehicle-to-vehicle standard communications… standards important here… this fuels the dream of fully autonomous vehicles.

Have software toolshelped automotive get this far?
A resounding YES and thumbs up to model-based design, design re-use, and tools that support huge projects with many people, distributed around the world.

Toshihide Tsuboi, Senior VP for MCU Business at Renesas,contributed a
perspective: Previously, in the first wave, minimizing fuel consumption, and emissions, were the main drivers for advanced electronics controls in automotive. The current frontier is functional safety, such as ISO26262 standards, and again MCUs must handle these challenges. Next, the exciting emerging area is ADAS, Advanced Driver Assistance Systems, which includes performance of MPUs for information handling, as well as sensors, displays, etc. At this time, no one really knows yet the amount and speed of information that will ultimately be involved in sophisticated ADAS, but it is increasing dramatically.

Takeaway: As Michael Grimes commented, electronics has made all the difference in the last few decades! Complexity up, power down. Great opportunity persists for automotive semiconductor and electronics companies who accurately gauge and respond to the trends…and thanks to Renesas DevConand all panelists for sharing the insights!

(Note: The above is paraphrased from notes, not verbatim, captured gist of remarks.)

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Power and Reliability Challenges

Power and Reliability Challenges
by Paul McLellan on 10-23-2012 at 12:38 pm
Categories: Ansys, Inc., EDA

Last week I attended the Ansys/Apache seminars on “Dimensions of Electronic Design.” The two big challenges as we go down to 28nm and 20nm and below are keeping power manageable and keeping reliability up.

The big challenge with power is that we can put so much stuff on a die and clock it so fast that the power is exceeding the capability of batteries (which only increases slowly, not exponentially) and even exceeding thermal limits of either the package itself or the system (think smartphone).

Noise is another huge problem. With higher drive devices the average current may only increase slowly but the transient current is going up much faster. In turn this leads to inductive effect with fast changing currents. But as the supply voltage comes down we can’t scale the threshold voltage much (for leakage reasons) meaning that the noise margin reduces every process node, although FinFETs may give a one-time kick since they have better leakage characteristics.

Another thing I had not realized is that in 28nm and below a lot of signal lines need to be analyzed for electro-migration (EM) effects. A minimum width metal line with a high-powered buffer violates the EM constraints.


An integrated power-centric design methodology needs to start with RTL power analysis. Getting the architectural decisions right has a much bigger effect than anything that can be done later tweaking things during physical design. Going forward, one thing that will increasingly be important is whether or not to use 3D chips with TSVs. This can have a huge effect on timing and power (because the distances are so much shorter). Although there are inaccuracies at the RTL level, they are smaller than might be expected and, besides, waiting until gates are available is too late in the design cycle.

Later, once physical design is done, a full analysis can be performed. This can include a whole spectrum of tests that are becoming more and more important:

  • off state leakage/voltage checks
  • inrush current (powering up blocks)
  • differential voltage checks
  • time to rampup (power up blocks)
  • noise coupling checks
  • switch id-sat check

Finally, the speeds and noise sensitivity of everything means that the chip, package, system must all be analyzed together, including the whole power delivery network with decaps etc. There is not enough margin to analyze each part separately and the risks are that it is underdesigned (aka fails) or overdesigned (aka too costly). Of course, if this is a 2.5D (interposer) or 3D design then this will need to be a multi-die analysis.

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Learning about MEMS in Israel from: EDA companies, Foundry, University, Users

Learning about MEMS in Israel from: EDA companies, Foundry, University, Users
by Daniel Payne on 10-23-2012 at 12:24 pm
Categories: EDA, Synopsys

In April I attended and blogged about a webinar on MEMS and IC co-design hosted by two EDA companies: SoftMEMS and Tanner EDA. On October 30th you can attend a full-day event in Israel that is more comprehensive than the webinar that I attended. Continue reading “Learning about MEMS in Israel from: EDA companies, Foundry, University, Users”

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Google Datacenter

Google Datacenter
by Paul McLellan on 10-22-2012 at 5:42 pm
Categories: General

In my blog about Intel’s latest results I linked to an interesting article in Wired about Google’s datacenters.

I happened to be browsing some websites in the Netherlands (actually I don’t speak a word of Dutch, a Dutch friend pointed it out to me) and there is an article showing how the pictures that accompany the Wired article have been photoshopped. You don’t need to be able to read Dutch to get the basic idea, the pictures are animated to show where one side of most of the pictures is cut and pasted from the other side (after reflection).

You can run the whole article through (irony of ironies) Google Translate to get a version in bad English (double dutch?).

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Hybrids on BeO then, 3D-IC in silicon now

Hybrids on BeO then, 3D-IC in silicon now
by Don Dingee on 10-21-2012 at 8:10 pm
Categories: Cadence, EDA

Once upon a time (since every good story begins that way), I worked on 10kg, 70 mm diameter things that leapt out of tubes and chased after airplanes and helicopters. The electronics for these things were fairly marvelous, in the days when surface mount technology was in its infancy and having reliability problems in some situations.

One of the problems with surface mount in the early going was the coefficient of thermal expansion, or more accurately the difference in CTE between the ceramic packages needed for defense-style temperature range requirements (-55 to +125C), and that of the FR-4 fiberglass most printed circuit boards were constructed from. With a few heating and cooling cycles, the ceramic packages would grow or shrink at a different rate than the board underneath them, stress the solder joints, and cause cracks or breaks. BGA, solder balls, and other fine pitch techniques were yet to be invented.

The solution for dense electronics in small places with wicked temperature extremes was hybrid microelectronic assemblies, and with some improvements in materials and process it still is today. The “for dummies” (and I resemble that remark) version:

1) Print the circuit on a ceramic substrate. At the time, the technology for substrates was beryllium oxide, viciously toxic in particle form when inhaled, but quite safe made into non-porous substrates. (One designer I worked with had a BeO coffee mug he drank from everyday to prove the point.) BeO also has super high thermal conductivity, providing a conduction cooling path. Today, you’re more likely to find aluminum nitride (AlN) in use.

2) Drop chips in raw die form onto the substrate in their proper locations.

3) Bond the pads on each chip to the corresponding pads on the substrate with thin gold wires – pretty much the same thing done inside a single IC package, except on a much larger scale with a lot of various dies and connections.

4) Put the finished circuit substrate into a Kovar metallic case, with I/O pins, and seal the edge with a weld so it’s hermetic.

5) Solder several hybrids to a flex harness providing interconnects between hybrids and connectors to other subsystems to make up the final assembly.

The lesson from electronics history is good ideas don’t go away when they are supplanted by innovation; they come back when a similar problem arises again on a smaller scale.

The idea of 3D-IC has been percolating for some time, and it’s the modern version of hybrids. The scale and materials are different, but as the TSMC name suggests – CoWoS, chip on wafer on substrate – it’s the same concept, minus wires and metal cases, and implemented completely in an EDA flow. This isn’t just to get more stuff in less space by better utilizing the Z axis, as the 3D name would imply. It’s about using the right process for the right function. Using silicon micro-bumping and through-silicon vias (TSVs) , a complete subsystem in proven silicon can be installed on a newly designed piece of 20nm digital logic. The EDA breakthrough will be making that a smooth flow instead of manual design and extra process steps.

With all the chatter about 28nm, 20nm, 14nm, and beyond, many folks might have lost sight that analog processes are no where near those geometries, and they don’t need to be. They are built out on mature, low risk, low noise process nodes. While analog is obviously involved in A/D and D/A converters, there are also MEMS sensors, and networking PHYs, and wafer-scale cameras and microphones that can all take advantage of a 3D process, without having to be redesigned into a cutting-edge geometry. Sematech summarized this nicely:

Memory subsystems are also becoming decidedly more analog in their signaling characteristics as speeds increase. Our Eric Esteve wrote earlier in a post discussing Cadence’s JEDEC Wide I/O mobile DRAM IP, and its target of 100Gbit/sec of DRAM bandwidth. Taiwan’s Industrial Technology Research Institute (ITRI) and TSMC both recently reported working with Cadence to tape out Wide I/O designs and prove out the new CoWoS flow.

If you missed the first round of hybrids, the idea is back, and it’s all in silicon this time. 3D-IC opens up a whole new range of possibilities for SoC design, not unlike what we’ve already seen at the microcontroller level on less aggressive process nodes with integrated mixed-signal EDA flow. The microcontroller-on-steroids with a much faster digital core, memory subsystems, and multiple analog I/O systems quickly and completely blending mature analog process nodes with advanced digital nodes is close at hand.

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Why Blog on SemiWiki.com?

Why Blog on SemiWiki.com?
by Daniel Nenni on 10-21-2012 at 7:00 pm
Categories: General

The Semiconductor Wiki Project, the premier semiconductor collaboration site, is a growing online community of professionals involved with the semiconductor design and manufacturing ecosystem. Since going online January 1st, 2011 more than 400,000 unique visitors have landed at www.SemiWiki.com viewing more than 3M pages of blogs, wikis, and forum posts. WOW!

Anybody can blog on SemiWiki and quite a few people do for personal fulfillment and professional enrichment.

Today everything and everyone is connected and crowd sourced. In fact, all social media, from blogs, to forums and wikis have a profound impact on how people communicate, search for information, and make decisions. Both personally and professionally, social media is no longer an experiment or a moonlighting function, social media is now an integral part of how we communicate.

Blogging is a life changing experience. Blogging is personal branding and can take you from relative obscurity to an internationally recognized industry professional. Blogging is mind expanding and develops communication skills you may never have known possible. One warning however, blogging is addictive. Once you turn it on it is very hard to turn off.

For me blogging is where I think, plan, and reflect. Blogging encourages me to research, gather credible information, and test hypotheses. Blogging is sometimes dangerous and nurtures my risk taking side but also extremely collaborative and provides a real-time feedback loop never before possible. Most importantly, my wife reads my blogs and now after 30+ years together she actually knows what I do for a living besides sitting in my La-Z-Boy with my laptop. She now knows what a semiconductor is, what EDA means, and why semiconductor IP is so important to our everyday lives.

As a SemiWiki blogger you will get personal invitations to industry conferences, seminars, and webinars. You will get exposure and access to semiconductor professionals at all levels, from CEOs to CTOs to engineers, marketing, sales, and public relations people, the entire semiconductor ecosystem at your fingertips.

5 things you should know about SemiWiki:

[LIST=1]

  • SemiWiki is global. Your experience here will be from around the world with an incredible amount of information at your fingertips. Make sure you connect and interact, make sure you engage at all levels.
  • Build relationships and network. You can truly connect here with people whom you have not met. Make friends and create a global support system for your professional life.
  • Take the good and the bad. Distinguish between fact and opinion, objective and subjective. People will either like or dislike your posts and there is something to be learned from both.
  • Don’t be evil. Top influencers will have one thing in common, they use their influence for the greater good.
  • Be yourself.Impersonating others online is a crime so just be yourself. Share your knowledge, share your profession, share your passion. You don’t have to be an expert or industry icon to be a top influencer on SemiWiki.

    Take control of your social media destiny, join SemiWiki and start blogging today! If you need further convincing feel free to contact me directly on LinkedIn http://www.linkedin.com/in/danielnenni It would be a pleasure to link to you and share my 13,000+ connections.

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    TSMC OIP Forum 2012 Trip Report!

    TSMC OIP Forum 2012 Trip Report!
    by Daniel Nenni on 10-21-2012 at 6:00 pm
    Categories: EDA, Foundries, TSMC

    The second annual TSMC Open Integration Platform Ecosystem Forum was last week and let me tell you it was excellent. Great update on the TSMC process technology road maps, great for networking within the fabless semiconductor ecosystem, great for seeing what’s new in EDA and IP, and great for SemiWiki. It was time well spent for sure. You can see my TSMC OIP 2011 trip report HERE for reference.


    The opening video was excellent this year! It was all about collaboration of course and an orchestra is a perfect example. My wife played first chair violin so this theme really clicked with me. Last year’s theme was a rowing team which did not click with me. You can see the symphony videoHERE.

    First up was Rick Cassidy. Rick is President of TSMC North America. Prior to joining TSMC in 1997 Rick was Vice President and General Manager of National Semiconductor’s Military and Aerospace Division. He joined National in 1979. Before that, Rick was an officer in the U.S. Army. He earned his Bachelor of Science degree from the United States Military Academy at West Point.

    According to Rick attendance was up from last year which I certainly agree with. I counted 1008 seats in the main auditorium and estimate that 95% of them were taken. This does not include the partners manning the booths in the exhibition room next door.

    Rick presented the TSMC vision and mentioned some interesting numbers:

    *TSMC has more than 5,000 silicon validated IP available today, WOW! I have been through the TSMC silicon validation process many times and let me tell you it is rigorous to say the least.

    *TSMC has invested $1.5B in design enablement thus far in 2012!

    *TSMC in 1987 had one fab, a $20M CAPEX, 30 products and shipped 3,600 wafers

    *TSMC in 2012 has 11 fabs, 5,498 different technologies, 12,569 products, $50B CAPEX, 615 customers, and a 15.3M wafer capacity!

    Rick mentioned that his decision to join the semiconductor industry was based on the opportunity to change the world. I wish I could say the same. 30 years ago I was a starving college student and my decision was financial. I knew there was big money to be made in Silicon Valley and I wanted some. Looking back however we did change the world and there is still plenty of money to be made in doing so.

    Next up was Dr. Mark Liu. Mark is TSMC’s Executive Vice President and Co-Chief Operating Officer. He joined TSMC in 1993 as an Engineering Manager. Prior to that Mark served in a number of technical capacities first with AT&T Bell Laboratories as a principal investigator in High Speed Electronics Research and later at Intel Corporation where he developed process technologies for Intel’s 32-bit microprocessors and flash memory products. Mark is a member of the Board of Directors of Silicon System Manufacturing Company in Singapore. He received Ph.D. degrees in electrical engineering and computer science from the University of California, Berkeley.

    I met Mark when I toured Fab 12 in 2010, I blogged about it HERE. A memorable experience for sure. Mark ramped up TSMC’s first 200mm fab in 1993 and has been building fabs for TSMC ever since. Mark talked about “The Internet of Things” and what 2030 will look like. Mark also stated that:

    *The TSMC 20nm design ecosystem (EDA and IP) are available today

    *20nm is close to complete and will be in production next year

    *TSMC will have three fabs for 20nm.

    Next up was Dr. Cliff Hou, Cliff is vice president of R&D. Cliff’s door and mind is always open for new technology discussions and debates on the future of the semiconductor ecosystem. Cliff joined TSMC in 1997 and was appointed TSMC’s Vice President of Research and Development (R&D) in 2011. He was previously Senior Director of Design and Technology Platform where he established the company’s technology design kit and reference flow development organizations. He also led TSMC’s in-house IP development teams from 2008 to 2010. Cliff holds 20 U.S. patents and serves as a board member of Global Unichip Corp. He received his Ph.D. in electrical and computer engineering from Syracuse University.

    Cliff added that:

    *20nm engagements with partners and customers started much earlier

    *TSMC overcame 20nm challenges through collaboration

    *16nm FinFET will require even deeper collaboration

    Cliff also mentioned that at 40nm partners and customers started design work when the PDK was release 0.5, at 28nm design work started at PDK 0.1, at 20nm design work started at PDK .05, and 16nm will start at PDK .01. The 20nm PDK 1.0 and 20nm foundation IP is silicon validated and available today with customer tape-outs expected in Q1 2013. 16nm PDK .1 will be available in Q1 2013 with the production version PDK 1.0 scheduled in Q4 2013.

    The most interesting thing for me was the FinFET discussions and there were plenty of them which I will blog about separately. For those of you who don’t know about FinFETS start here with the FinFET Wiki. 2013 will be the year of the FinFET, absolutely!

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    A Brief History of Aldec

    A Brief History of Aldec
    by Daniel Payne on 10-20-2012 at 5:31 pm
    Categories: Aldec, EDA

    Dr. Stanley Hyduke founded Aldecin 1984 and their first product was delivered in 1985, named SUSIE (Standard Universal Simulator for Improved Engineering), a gate-level, DOS-based simulator. The SUSIE simulator was priced lower than other EDA vendor tools from the big three: Daisy, Mentor and Valid (aka DMV). Aldec maintains a global network of regional offices and is the only EDA company to have Corporate Headquarters located in Nevada.

    Continue reading “A Brief History of Aldec”

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    DAC: It’s the Last Week for Many Submissions

    DAC: It’s the Last Week for Many Submissions
    by Paul McLellan on 10-19-2012 at 2:36 pm
    Categories: EDA, Events

    The deadline is coming up at the end of next week (technically on Monday October 29th for those of you who like real brinkmanship) for several aspects of DAC (not submission of papers for the conference itself) but most of the less academic-oriented things.

    Proposals for:

    • Special Sessions
    • Tutorials
    • Panel sessions (in the conference itself)
    • Pavilion panel sessions (in the exhibit hall)
    • Workshops

    must all be submitted by the 10/29 cutoff.

    One of the things I think has been a really big positive for DAC was creating the Pavilion in the exhibit hall. The pavilion panel sessions are usually really interesting and presentations are often standing room only. I’m sure next year will be the same and if you have good ideas for pavilion panel sessions then next week is the time to get them down on paper.

    For those readers who are also DAC exhibitors there is also a (not compulsory) meeting a week or so later on Wednesday November 7th. DAC is in Austin next year (you knew that, right?) but this meeting is 3.30-4.30 on 11/7 in the San Carlos Room at the Hilton San Jose (the one by the convention center). They’ll tell you what is planned and take suggestions for other stuff they should be planning.

    And for those of you that really like to plan ahead, the 51st and 52nd DACs are both in San Francisco from June 1-5 2014 and June 8-12 2015. Put them on your calendar. That gives me plenty of time to do extensive research to update my blogs on what are the best bars and restaurants to visit during DAC.

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    Intel Quarterly Report: Needs to Do Better

    Intel Quarterly Report: Needs to Do Better
    by Paul McLellan on 10-19-2012 at 11:51 am
    Categories: Foundries, Intel Foundry

    Intel announced its quarterly results a couple of days ago. They had previously downgraded 3rd quarter sales estimates but they managed to beat the downgraded numbers. If you look at the transcript of the call (I didn’t listen live) you’ll see very little mention of mobile and Atom. This is bad news for Intel. Its core business is the PC and the PC business is going nowhere. Not going away but it is not going to be the catalyst for future growth.

    Intel’s sales in Q3 were down 5% from 2011Q3 and flat from last quarter. There is some short-term hope with Windows 8 driving an imminent corporate PC upgrade cycle. But overall PC sales are forecast to fall in 2012 versus 2011. Some of that can be blamed on the weak economy (“not many sales in Greece”, actually nobody said that).

    Looking under the PC hood, datacenter revenue is up 6% on 2011Q3 but down from Q2. However, the client part (notebooks, desktops etc) is down 8% from 2011Q3. In fact someone told me anectdotally that the biggest end-user of Intel chips is Google. And it wouldn’t surprise me if Amazon, Apple, Oracle, Salesforce and the rest of the big datacenter crowd are not in other top spots. They are increasingly worried about energy efficiency of computation and a general purpose high-power processor is not the sweet-spot, it is the easiest to manage spot.

    Intel’s big challenge is that it can see that the PC market is in secular decline outside of the datacenter. There are also storm clouds on the datacenter that might eventually impact even that revenue. Read the Wired article about going inside Google’s datacenter (they’ve fixed the funny captioning where they called a cooling plant the server room and vice-versa) and you’ll see this quote:So far, though, there’s one area where Google hasn’t ventured: designing its own chips. But the company’s VP of platforms, Bart Sano, implies that even that could change. “I’d never say never,” he says. “In fact, I get that question every year. From Larry.”

    If your largest end-user is thinking about designing you out, you worry. And there are similar stories about Apple designing their own microprocessors, perhaps even picking up AMD for a bit of its spare change to avoid legal hassles.

    Intel’s Ultrabook program (MacBook Airs that runs Windows) doesn’t seem to be getting a lot of traction yet although some of them look very…well, just like a MacBook Air. But they are not compellingly cheaper. I wouldn’t want to pretend that a hipster coffee shop in the Mission in San Francisco is representative of the world, but you never see anything but Apples in there. It is not clear if they are competing with a MacBook air or an iPad anyway.

    Intel’s big problem is mobile. And the problem is two-fold. Firstly, Intel isn’t yet a force in mobile although it does have a few wins. Secondly, even if it won large market share I don’t see how it can survive on the margins they would get. This is made worse by the fact that Apple and Samsung take all the profit in handsets. Samsung is not going to stop building their own chips so they are ARM (or at least not Intel) forever. Apple is not going to change from ARM probably ever, but even if they did it would not be on the basis that Intel gets their traditional PC margins on whatever Ax it is.

    So what about Intel’s manufacturing lead? It is certainly real at 22nm, they are shipping product in volume and nobody else is. I know nothing about Intel’s costs but in the merchant foundry industry all the evidence is that 20nm is going to be much more expensive that 28nm. Perhaps 4X the cost for a wafer, so around 2X cost for the same functionality. That will come down over time, probably, with process learning and yield improvement but I doubt it will get compellingly below 1, meaning 28nm will be roughly the same cost. If Intel’s costs are similar, that is fine for the datacenter business which can withstand the cost to get the functionality but will not work for the smartphone business. Especially at the low end, the sub $100 smartphone.

    Fundamentally, Intel assumed that whatever came after the PC, Windows binary compatibility, especially Microsoft Office, would be the key to the future and only they owned the lock. But that doesn’t seem to be true. As I wrote a few years ago (in pre-iPad days when the post PC device was still being called a netbook):”My gut feel is that the netbook will be more like a souped up smartphone than a dumbed down PC and so Atom will lose to ARM. The smartphone and netbook markets will converge. Microsoft will lose unless it ports to ARM. There will be no overall operating system winner (like smartphones).”

    Apart from changing out the term “netbook” there is not much to change about that, and some has already come to pass.